Fault-tolerance has become a first-class design constraint in many real-time and embedded systems designs, in arenas ranging from avionic / automotive systems and satellites to distributed systems including IoTs, medical instrumentation and even consumer electronics. Designs of all these systems necessitate mechanisms for obtaining pre-specified quantitative levels of reliability. However, in order to achieve such reliable designs, system development process must go through several phases including specification, design, implementation, verification and testing. The principal objective of this short-term course is to systematically provide a theoretical overview of the steps involved in these phases. The coverage is kept wide, but brief, to include all the phases.

Due to the immense importance of this topic especially in the modern era, many technical institutions in India are developing and offering their own courses fault-tolerant systems. However, most of these courses do not have exposure to all the phases (limited, mainly to design) without much exposure to the basic theory and CAD tools. Many other issues starting from correct specification and modeling, hardware-software partitioning, appropriate hardware architectural design, system level timing validation, memory design and scheduling, interrupt handling, tackling interference among multiple applications competing for limited shared resources etc., need equal emphasis. This course will not only give proper directions to the attendants (teachers) towards formulating detailed UG and PG level courses along with appropriate laboratory support, but also provide a strong impetus towards innovation sensitization along with innovative technology development in the area of fault-tolerant embedded systems design, especially in the eastern and north-eastern part of India.

• Dr. Chandan Karfa, Assistant Professor, IIT Guwahati.
• Dr. Arnab Sarkar, Associate Professor, IIT Guwahati.
• Dr. Soumyajit Dey, Assistant Professor, IIT Kharagpur.
• Dr. Aryabratta Sahu, Associate Professor, IIT Guwahati.
• Dr. John Jose, Associate Professor, IIT Guwahati.

• Day 1: Fault Tolerant Systems I:Introduction, Fault Classification, Types of Redundancy, Real-time Fault Tolerant Systems and Fault Models.
• Day 2: Fault-Tolerant Systems II: Fault Tolerant Scheduling, Hardware and software fault tolerance, Information redundancy, Check pointing.
• Day 3: Fault-tolerant Networks: Measures of Resilience, Network Topologies and their Resilience, Fault-tolerant Routing strategies; Mixed-Criticality Systems: Introduction, Single processor analysis, Multiprocessor analysis, Realistic models, formal treatments and systems issues.
• Day 4: Fault Tolerant system models. Formal Verification Basics: Model Checking, Symbolic Model Checking, Bounded Model Checking, SMT Solvers.
• Day 5: Formal Approaches to modeling and control of fault-tolerant systems. Pedagogy session.

The course is open to faculty members of TEQIP mapped institutions. Please refer to "Institution List" link in the NPIU website for list of TEQIP mapped institutions. However, PhD scholars/PG students from these institutions may be accommodated subject to the vacancy of seats. There will be a refundable registration fee of 2500 INR for the participants from TEQIP mapped institutions. Seats that remain unfilled will be open to faculty/students of other institutions with a non-refundable registration fee of 2500 INR. There will be a total of 40 seats for the course based on application followed by shortlisting. The registration fee will cover course materials and working lunch.

1. Take a Demand Draft of 2500 INR drawn in favour of Registrar, IIT Guwahati, payable at Guwahati towards registration fee.
2. Download the course Application Form and fill-up (typesetting is preferred over handwritten) all the entries including DD details.
3. Generate a pdf document of the filled up application form and take a printout of the same.
4. Affix your recent passport size color photograph and put your signature in the respective cells.
5. Download the course Endorsement Form and get it duly approved and signed by the head of your institution. Seal of the institute is mandatory.
6. Send the documents and DD via speedpost to the course cordinator (postal address given below) so as to reach IIT Guwahati latest by 21.06.2019, Friday.
7. Send a soft copy (preferrably pdf) of the duly filled application form to debabratasenapati@gmail.com.
8. Fill this Intimation Form after you have send the application form and the DD via post.

List of selected candidates from TEQIP mapped institutions will be displayed on this website by 25.06.2019. No separate emails will be sent regarding this.
List of selected candidates from non-TEQIP institutions will be displayed on this website by 27.06.2019. No separate emails will be sent regarding this.
Registration Fee DD will be returned back (via speed post), if the candidate is not shortlisted.

For participants from TEQIP mapped institutions, based on request, accommodation can be arranged free of cost either in the student hostels inside IITG campus or in hotels at Guwahati city. Participants from non-TEQIP institutes should make their own arrangements for boarding and lodging.