EE 210	Digital Circuits	3-0-0-6
Syllabus: Gate level combinational circuits: multiplexer/ demultiplexer, encoder/ decoder, adder/ subtractor, comparator and parity generators; Gate level sequential circuits: latches and flip-flops (RS, JK, D, T, and Master Slave); Registers; Counters: ripple, ring, and shift register counters; Design and analysis of synchronous sequential finite state machine; Memory and Programmable logic devices; Digital CMOS circuits: CMOS inverter: operation, VTC, propagation delay and power dissipation; Static CMOS circuits: rationed, pass transistor and transmission gate logics, latches and registers; Hardware description language: types, constants, arrays, functions and procedures; Examples on structural, data flow and behavioral designs. Texts/References [1] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits - A Design Perspective, 2nd edition. PHI, 2016. [2] C. H. Roth Jr. and L. L. Kinney, Fundamentals of Logic Design, 7th edition. Cengage Learning, 2014. [3] M. M. Mano and M. D. Ciletti, Digital Design, 4th edition. Pearson, 2011. [4] P. J. Ashenden, Digital Design - An Embedded System Approach using Verilog. Elsevier, 2010. [5] Z. Kohavi, Switching and Finite Automata Theory, 2nd edition. Tata McGraw-Hill, 2008. [6] V. A. Pedroni, Digital Electronics and Design with VHDL. Elsevier, 2008. [7] J. F. Wakerly, Digital Design - Principles and Practices, 4th edition. Pearson, 2006.