Course Structure:

• Pre-Mid Sem Part: Boolean Algebra and switching functions; Minimization and realization using logic gates, ROMs, PLAs, multiplexers; Circuits for code conversion;
• Post-Mid Sem Part: Flip-flops, registers, counters; Finite state model: State tables and diagrams; State minimization; Excitation functions of memory elements; Synthesis of synchronous sequential circuits; Representation and synthesis using ASM charts; Incompletely specified machines; Specification and synthesis of asynchronous sequential machines; Number representation: fixed and floating point; Addition, subtraction, multiplication and division of numbers. Current trends in digital design: ASIC, FPGA, etc.;

Lectures: Pre Mid Sem part

---

1. 24 Jul 2018 (TUE): Introduction to Digital Design (Course, Grading Procedure, Rules, Quiz, Text Books) PDF Slides
2. 25 Jul 2018 (TUE): Introduction to Number System and Digital System PDF Slides (same as Lec01)
3. 30 Jul 2018 (MON): Number System, Operations (add, sub, mul, div), 2's complement, use of 2's complement in substraction and multiplication; Basic gates; Intro to Boolean Algebra PDF Slides
4. 31 Jul 2018 (TUE): Boolean Algebra, Axioms and Theorems PDF Slides
5. 01 Aug 2018 (WED): Logic Gates and Boolean Algebra, SOP and POS form PDF Slides
6. 06 Aug 2018 (MON): QUIZ 1 and MultiBit Adder, Hamming Distance and Gray Code Quiz 1

---



7. 07 Aug 2018 (TUE): Minimization of Switching Functions and KMaps POS/SOP and KMaps
8. 08 Aug 2018 (WED): KMaps and Quin-McCluskey Method KMaps and QM Methods
9. 13 Aug 2018 (MON): Comparison and Relation between K Map Method and QM Method, Comb. Logic Design (Encoder, Logic function using Encoder) PDF Slides (1 page/slide)
10. 14 Aug 2018 (TUE): Decoder (N to 2^N, Memory Addressing), Encoder (2^N to N), Priority Encoder, Multiplexor (2^N to 1, N select lines), Function Implementation with Decoder and Multiplexor, Designing Configurable Logic Block (CLB) with Mux and Look up Table (LUT)/Truth Table, and Mux/Decoder with Enable PDF Slides [Ref: Chapter 4 of Mano Book]


11. 20 Aug 2018 (Mon): Binary ADDER/SUB, BCD ADDER, Multiplier, Array Multiplier, Delay and Area complexity PDF Slides [Ref: Chapter 4 of Mano Book]
12. 21 Aug 2018 (TUE): QUIZ 2 CLB and Arithematics Quiz 2

---



13. 27 Aug 2018 (MON): N Bit Adder (RCA, Manchester Switch Adder, Carry Skip Adder, Carry Select Adder, Carry Look Ahead Adder) PDF Slides [[Ref: http://web.cs.ucla.edu/digital_arithmetic/files/ch2.pdf]]
14. 28 Aug 2018 (TUE): Binary Multiplier (Seq, Booth, High radix) PDF Slides
15. 29 Aug 2018 (WED): Programmable Logic Devices (PAL, PLA, ROM, PROM, SRAM-cell, SRAM) PDF Slides [[Ref Chapter 7 of Mano Book]]
16. 03 Sep 2018 (MON): SPLD, CPLD, FPGA and FPGA Flow PDF Slides
17. 04 Sep 2018 (TUE): Verilog HDL and Examples PDF Slides
18. 05 Sep 2018 (WED): QUIZ 3 ...

---

[[Verilog HDL Book by Palnitkar]]


19. 10 Sep 2018 (WED): Verilog (Data Flow, Structural and Behavioral code) PDF Slides
20. 11 Sep 2018 (WED): Module instantiations and inter connection, Verilog Procedures (always and initials, if else, case, while, repeat, delay, fork-join), Test Benches, Many Examples: 4 bit RCA and 4x1 Mux. Many coding style of 4x1 Mux PDF Slides

---

Text Books:

1. ManoBook: M. Morris Mano and M. D. Ciletti, Digital Design, 4/e, Pearson Education India, 2007.
2. KatzBook: Randy H. Katz, G Borriello, Contemporary Logic Design, 2nd Edition, PHI, India, 2009
3. KumarBook: A. Anand Kumar, Fundamentals of Digital Circuits 3rd Edition, PHI. 2014 ((This book have a lot of examples to understand the concepts))

1. Tomas Lang, Jaime H. Moreno and Milos Ercegovac Introduction to Digital Systems, Wiely India Edition, 2009
2. Givone Book: Donald D. Givone, Digital Principles and Design, McGraw-Hill, 2003
3. VahidBook: Frank Vahid, Digital Design (Preview Edition), Wiely India Edition, 2005
4. Palnitkar: Samir Palnitkar, Verilog HDL Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition, Prentice Hall, 2003 PDF Book

Class timing, Venue and Rules:

• Venue: 1207, Timing: Mon 9 AM-10 AM, Tue 10 AM-11 AM, and Wed 11 AM-12.00Nn
• Weightage : Mid Sem 30%, 3 Quizs 10% (Before Mid), End Sem 60% (includes 10% of PreMid Parts), One Surprize Quiz in Post mid Sem part (Bonous Weightage)
• Premid sem Quizs will be on 6th, 12th and 18th classes, carrying 3%, 3% and 4% Marks respectively