Course Structure:

• Instruction sets. RISC and CISC paradigms. Various addressing modes. Assembly language programming of at-least one of the existing systems.
• Arithmetic and Logic Unit. Instruction interpretation: Micro-operations and their RTL specification

Mid Semester Examination


• CPU design: Hardwired and Microprogrammed.
• Memory Organization, I/O transfer: Program controlled, Interrupt controlled and DMA.
Introduction to computer buses, peripherals, performance benchmarking and current trends in architecture.

Lecture Slides:

1. 28 Dec 2010 TUE: Introduction Computer Organization and Architecture PDF Slides
2. 31 Dec 2010 FRI: History of Computer System and Instruction Set Architecture PDF Slides
3. 03 Jan 2011 MON: Introduction to MIPS Instruction Set (Arithmetics, Register, Memory,Load/Store) PDF Slides [[[ SPIM/MIPS User Manual, Appendix A of Hennessy Paterson Book]]]
4. 04 Jan 2011 TUE: Introduction to MIPS Instruction Set (Type of Instruction(R,I,J), Constant, Branch/Control) PDF Slides
5. 07 Jan 2011 FRI: MIPS Assembly Language Program, Memory layout, Array/Pointer and SPIM Simulator PDF Slides Programming Assignment 1


6. 10 Jan 2011 MON: Procedure Call/Return, Parameter Passing, Activation Record/Frame Pointer, Recursive Call PDF Slides
7. 11 Jan 2011 TUE: Merge Sort Activation Record, Addressing Modes, RISC Vs CISC PDF Slides
(Programming Assignment 2)
8. 14 Jan 2011 FRI: RISC Vs CISC, SPARC, PowwerPC and VAX PDF Slides


9. 17 Jan 2011 MON: X86 ISA and Boolean Arithmetic, Integer/Floating Point, Addition/Substraction PDF Slides
10. 18 Jan 2011 TUE: Boolean Adder Algorithms PDF Slides [[[Supplementary Material:http://www.cs.ucla.edu/digital_arithmetic/files/ch2.pdf]]]
11. 21 Jan 2011 FRI: Adder ContinuedPDF Slides [[[Chap2, Digital Arithmetic, Ercegovac/Lang, Morgan Kauffman,2004 ]]]
12. 24 Jan 2011 MON: Multiplication and Division PDF Slides [[[ Chap 3- Hennessy Book, Chap 6- Hamachar Book]]]
    
13. 27 Jan 2011 THU (Makeup): Multiplication and Division Continued PDF Slides Booth Algorithm, Chap 9 Stalling
    
14. 28 Jan 2011 FRI: IEEE Floating point(single,.double), representation, density, error PDF Slides [[[Chap 3- Hennessy Book, Chap -9 Stalling Book ]]]


15. 31 Jan 2011 MON: Floating point arithmetic and Data Path for arithmetic instruction PDF Slides
16. 01 Feb 2011 TUE: Data Path for Arith/LD/ST/CTR instruction PDF Slides [[ Hennessy 3rd Edition Book, Sec 5.4/Sec 4.4 of 4th Ed Book]]
17. 03 Feb 2011 THU:(Makeup Class) Data path Design Methodology, Control Path and Performance PDF Slides
    Programming Assignment 3

No Class From Feb 7 to Feb 14

18. 15 Feb 2011 TUE: Control Path for Single Cycle CPU PDF Slides
19. 17 Feb 2011 THU:(Makeup Class) Multi Cycle CPU Design (Data Path) PDF Slides [[ Hennessy 3rd Edition Book, Sec 5.5]]
20. 18 Feb 2011 FRI: Multi Cycle Design Data Path + Control PDF Slides
    

Mid Semester Exam: 10.00AM-12.00Nn, 23Feb2011, L2/L3 Question Paper CS222mid.pdf, Model SolutionCS222midModSolution.pdf

21. 28 Feb 2011 MON: Pipelined processor: (Performance, Hazards) PDFSlides
22. 01 Mar 2011 TUE: Pipeline Hazards: Resource and Data PDF Slides

04 Mar 2011 FRI: Mid Sem Paper Evaluation, Model Solution, Discussion and Grading CS222midModSolution.pdf


23. 07 Mar 2011 MON: Pipeline hazards: Data Hazards, Pipeline Stall, Data Forward Paths Contd.. PDF Slides [Sec 4.7 of 4th Edition Hennessy Book or 5.7 of 3rd Edition Hennessy Book ]
24. 08 Mar 2011 TUE: Pipeline Hazards: Control/Branch Analysis (Pipe Stage, Clock timing, branch) PDF Slides [[[Sec 4.7 of 4th Edition Hennessy Book or 5.7 of 3rd Edition Hennessy Book, Sec 2.2 of Flynn Book]]]
25. 11 Mar 2011 FRI: Pipeline Hazards: Control/Branch Analysis (Branch Elimination, Branch Speed Up, Branch prediction, Branch Target Capture) PDF Slides [[[Sec 4.5 of Flynn Book ]]]
26. 14 Mar 2011 MON: Pipeline Hazards: Control/Branch Analysis (Branch Elimination, Branch Speed Up, Branch prediction, Branch Target Capture PDF Slides
27. 15 Mar 2011 TUE: Pipeline: Super-scalar and VLIW processor PDF Slides [[Advanced Comp. Arch (A Design Space Approach)By D. Sima et al,Pearson Education India ]]

Take Home Exam 1 (Submission time 21 Mar 2011 Monday 10AM-11AM, if u submit after Monday credit will be zero): Submit a concise 10-12 pages handwritten report on super-scalar processor issue, decoding, shelving, dispatch, renaming and ROB. You can refer/read any book or web material but put proper references (for copied diagram and copied paragraph) in your report.


28. 18 Mar 2011 FRI: Super-scalar and Memory Hierarchy Introduction PDF Slides
29. 21 Mar 2011 MON: Cache Part I: Memory Hierarchy, Hit/miss, Direct mapped, Associativity PDF Slides
Assignment 4 on memory hierarchy
30. 22 Mar 2011 TUE: Cache Part II: Example Program Cache Behaviour PDF Slides
31. 25 Mar 2011 FRI: Cache Access Time, Multi Level, Indexing PDF Slides
32. 28 Mar 2011 MON: Cache Policy (Read/Write/Load/Fetch/Replacement) PDF Slides[[Ref: Memory Systems And Pipelined Processors, Narosa Publishing House (1998), Rs 228, Chap 2-4 ]]
33. 29 Mar 2011 TUE: Cache Performance Improvement (I) PDF Slides [[Sec 5.2, Comp.Arch-A Quantitative Approach, Hennessy Patterson Book, 4th Edition]]
34. 01 Apr 2011 FRI: Cache Performance Improvement (II) PDF Slides


35. 04 Apr 2011 MON: Memory SDRAM/DRAM, Disk PDF Slides
Take Home Exam 2 (Submission time 14 Apr 2011 Thursday 9AM-10AM, if u submit after Thursday credit will be zero): Submit a concise 10-12 pages handwritten report on Advanced Memory Addressing Scheme (Virtual Addressing, TLB, Paging and Segmentation). You can refer/read any book or web material but put proper references (for copied diagram and copied paragraph) in your report.

36. 05 Apr 2011 TUE: Hard Disk Access PDF Slides
37. 08 Apr 2011 FRI: Virtual address and Paging PDF Slides



38. 11 Apr 2011 MON: IO Organization PDF Slides
39. 12 Apr 2011 TUE: Grand Four IO Controller :PPC, PIT, PIC and DMA PDF Slides
40. 18 Apr 2011 MON: Concluding Class PDF Slides

Assignments:

Please visit SPIM official website : http://pages.cs.wisc.edu/~larus/spim.html

• Assignment 2: MIPS Assembly Programming 2 (10 marks) Announced Date: 12 jan 2011
  • Statement:Complete the assembly program for recursive merge sort.
  • Phase 1:Write a pointer version (C and assembly)
  • Phase 2: Include code to track the max stack size, Reduce local array size to n and find improvement (in stack size reduction)
  • Phase 3:Write more space efficient program (C and assembly), still recursive
  • Deadline: 24.Jan.2011, 11.55 PM (before Mid night), Copy Case Lead to F Grade.
  • After deadline grading: Maximum X marks out of 10 marks scale
  • Submission procedureSend both C programs, and Written ALP to asahu AT iitg DOT ernet.in with “CS222 Assignment 2” as subject
  
  
  
• Assignment 1: MIPS Assembly Programming 1 (10 marks) Announced Date: 7 Jan 2011
  • Statement:Write and execute MIPS assembly language program to Read a String and print the String in reverse order.
  • Phase 1:Write a C Program array version to do above work, Write the same C program pointer version
  • Optional Phase 1.5: Download MIPS GCC, install, generate MIPS code from your C Program to view
  • Phase 2: Write a MIPS Assembly Language Program Pointer Version and run on SPIM Simulator
  • Deadline: 16.Jan.2011, 11.55 PM (before Mid night), Copy Case Lead to F Grade.
  • After deadline grading: Maximum X marks out of 10 marks scale
  • Submission procedureSend both C program, GCC Generated ALPs and Written ALP to asahu AT iitg DOT ernet.in with “CS222 Assignment 1” as subject
  
  
  

Books:

1. Patterson, D.A., and Hennessy, J.L. , “Computer Organization and Design: The Hardware/Software Interface”, Morgan Kaufmann Publishers, 4th Edition, Inc.2005 (Very Good Book to Purchase and Keep a Copy with You)
2. Patterson, D.A., and Hennessy, J.L. , “Computer Architecture : A Quantitative Approach ”, Morgan Kaufmann Publishers, 4th Edition, Inc.2005 (Very Good Book to Purchase and Keep a Copy with You)
3. Hamacher, V.C., Vranesic, Z.G., and Zaky, S.G., “Computer Organization”, 5/e. McGraw-Hill. 2008
4. Tanenbaum, A.S, “Structured Computer Organization”, Prentice-Hall of India. 1994
5. Stalling W, “Computer Organization and Architecture ”, Pearson Eduction India. 2008

1. D V Hall, Microprocessors and Interfacing, TMH, 1995
2. Brey. Barry B, The Intel Microprocessors 8086/8088, 80186/80188, 80286, 80386, 80486, Pentium, and Pentium Pro Processor Architecture, Programming, and Interfacing, Prentice Hall India, 2005

Class timing, Venue and Rules:

• Venue: 1201
• Timing : Slot C { MON:10AM–11AM, TUE:11AM-12Nn, FRI:9AM-10AM, (Skipping/Makeup THU:8AM-9AM) }
• Rules :
  • 75% attendance mandatory
  • Attendance will be calculated before end semester examination
  • 15% Assignment + 40% mid term+ 45% end term