CS223 : Hardware Lab Jan 2014- Apr 2014

Instructor: Dr A Sahu

Group structure of CS223 Group Structure & Marks
Demo and Help Files for PC-FPGA-USB communications
VHDL lecture slides (Lecture 31 to Lecture 34) of CS221 course: http://www.iitg.ernet.in/asahu/cs221/
Update for Last Assignment: If you are not comfortable with floating point, you are allowed to go for integer data in matrix multiplication. Use integer operation in low pass filter. In K-mean/centroid project: people may infer 4 to 5 pipeline floating point unit (multiplier and adder) using LOGIcore IP generator
VHDL lecture slides (Lecture 31 to Lecture 34) of CS221 course: http://www.iitg.ernet.in/asahu/cs221/


Assignments
  1. Experiment 1 (Weightage=18Marks, Time 9 lab hour : Demo will be on 3rd Lab (on 17th Jan 2014))
    Demonstration of working of 4 bit ALU     [[Motivation: Experiment with Digital Components]] Assignment Statement (PDF)

    1. [30% Mark] Demonstrate functionality of a 4 bit ALU chip using breadboard. You are allowed to use 7 segment LED and driver to show/demonstrate the output. Some ALU operations require two operands of 4 bit, you can assume/provide a fix value for an operand (Ex 2+A, 2-A, here 2 is a fixed number and A is an input).
    2. Design VHDL model and simulate for the bellow given components in Xilinx ISE and finally download your design to Spartan 6 FPGA board.
      1. [10% Mark] 4x16 decoder
      2. [15% Mark ] 4 bit and adder/substractor
      3. [45% Mark ] 4 bit ALU with 4 control inputs (similar to ALU chip available in our Lab)

      You may interface one or two register to store inputs for your design.

    You can take help from TAs. All the TAs and Instructor of CS223 will be available in lab timing. You can ask TAs or Raktajit Pathak about license and installation of ISE software. Bread board and required ICs may be issued from Hemanta Nath.

    Grade will be based on (a) Correctness, (b) Quality of design, (c) Wire optimization, (d) Optimum number of chip used,(e) Cleanliness in design (Wire and Chips should be organized to look good), (f) Use of proper Comment/Naming/Labeling of the wires and (g) Questionnaire and explanation.
  2. Experiment 2 (Weightage=20Marks, Time 9 Lab hour : Demo date 7th Feb 2014)
    Design and Implementation of a 8 bit unsigned integer multiplier and demonstrate functionality on both FPGA [[10 marks]] and Breadboard [[10 marks]] ---------------Repetition of last year assignment :) :)----

    One method of multiplication (Block diagram and Pseudo code to multiply two n bit numbers) is given bellow (you are allowed to discover/choose other methods like repeated additions, partial addition, etc):

    Suppose we want to multiply A (8 bits) and B (8 bits), and store result at S. Number of bit required for output S is 16 bits. S have higher part SH and lower part SL. As shown in Pseudo code, initially place B in SL (operation S=0|B) and run the while loop of shifting S and increment i. In each step, if S0 (right most bit of S) is set then add will be activated.

    In this, we require a n bit Adder/ALU, 2n bit S with Parallel IN/OUT/RightShift operations. And to do control, we require a log(n) bit counter and a AND Gate.

    Some hints for breadboard implementation:
    1. 8 bit adder can be designed using two 4 bit adder/ALU
    2. 16 bit S register can be designed using 2 four bits PIPO shift register and one 8 bit SIPO (and-or one 8 bit PISO) register.
    3. Controller can be designed using a Modulo 8 Counter or 3 bit counter and an AND Gate
    4. You have to display result S (16 bit) onto two Seven Segment Display using 3 quad 2 input MUX. Either you can use three bit (Octal) display format or 4 bit BCD fix garbage mode.
    5. Use 8 pack DIP switches to provide input to your Multiplier
    6. After you store B into SL you may required to deactivate inputs to B.
    7. Grade will be based on (a) Correctness, (b) Quality of design, (c) Wire optimization, (d) Optimum number of chip used, (e) Cleanliness in design (Wire and Chips should be organized to look good), (f) Use of proper Comment/Naming/Labeling of the wires and (g) Questionnaire and explanation.

    Some hints for FPGA implementation:
    1. Design a 16 bit efficient adder
    2. Design a 16 bit PIPO Shift Register and one 8 bit PIPO register
    3. Controller can be designed using a Modulo 8 Counter or 3 bit counter and an AND Gate
    4. Provide inputs to 8 bits multiplier in phase wise. Store inputs to registers in phases wise.
      There are 8 LEDs, 6 buttons and 8 slide switches GPIO in Atlys™ Spartan-6 FPGA Development Board. So you can utilize slide switch for input 8 bits and button switches for clock/control. Also it the time of displaying again utilize button switch to control output (the SH and SL) to LEDs
    5. Grade will be based on (a) Correctness, (b) Quality of design, (c) LUTs used, (d) Register/Wire used (e) Cleanliness in design , (f) Use of proper Comment/Naming/Labeling of the wires/signal and (g) Questionnaire and explanation.

    Reference
    1. M. Morris Mano, “ Digital Design”, 4th Edition, Pearson Education India, Chap 8, Sec 8.7 Sequential Binary Multiplier
    2. Patterson, D.A., and Hennessy, J.L. , “Computer Organization and Design: The Hardware/Software Interface”, Morgan Kaufmann Publishers, 4th Edition, Inc.2005, Chap 3 Sec 3.3 Multiplication
    3. iitg.ernet.in/~asahu/cs221/ or iitg.ernet.in/asahu/cs221/Lects/Lec27.pdf
  3. Experiment 3 (Weightage=20Marks, Time 9 Lab hour : Demo date 8th March 2014 (Saturday))
    Memory and PC interfacing to FPGA
    Main aim of this assignment is to interface FPGA Spartan-6 with host computer via USB and inferring Block ram of FPGA. Also this experiment allow you understand about BUS interface.

    Design an host computer interface (as described in www.dejazzer.com/ee478/labs/lab8_usb_fpgalink.pdf or Local Copy of usb_fpgalink.pdf ) and do the following

    1. Sent N 8 bit numbers to FPGA and store in Block RAM of FPGA
    2. Access all number one by one and add all the numbers sequentially using a 8 bit adder
    3. Display the lower 8 bits of result on LEDs of FPGA and also return the result (more than 8 bits) from FPGA to PC and display in host computer

    As shown in bellow diagram, you may require to use two 8 bit bus. One is data bus other is address bus. Multiple people read from the BUS simultaneously but only one should write to BUS at a time (Use Tristate Logic). (another way: suppose 8 people are trying write to bus, you can use a 3x8 decoder to select the Person for write operation to BUS)


    FSM Steps

    Step 1: A=0; // Clear Ac=1;
    Step 2: UCTR=0;
    Step 3: while (UCTR Step 5:    T=M[UCTR]; // Mout=1; Tin=1; UCTRout=1;
    Step 6:    S = A +T; if (A > 15) AH++; // AHC=1, ADD=1, Sin=1;
    Step 7:     A = S; UCTR++; // UC=1, Sout=1, Us=1; Ds=1;
                  }
    //Where AHC (Add High Carry), ADD, Sin (SumWrite), Tin (TempWrite), Tout (TemoRead), UC, Sout (SumRead), Us, Ds, M2BDin (MemoryToDataBusWrite), A2DBin (AtoDataBusWrite), P2Bin (PCToDataBusWrite), 02Abin and U2ABin are control signals

    In this experiment, you need to write code for RAM (Block RAM inferable code) and for a 8 bit adder.

    Hint:
  4. Experiment 4 (Weightage=42 Marks, Time 18 Lab hour : Demo date (Read Assgn4.pdf)
    Design and Implementation of Compute Accelerator using FPGA
    5. Main aim: Many application/problem have best execution time complexity of order N4 or N3 or even N2 but this execution time may not acceptable for some case. If the application/problem is highly/massively parallel, FPGA provides an efficient way to reduce the execution time without minimizing the time complexity. FPGA based systems are one or two order faster as compared to CPU, means speed up up to 10 or 100 can be achieved.

    FPGA accelerator are used in many application like computer vision, gzip, data analytic, machine learning, network intrusion detection, packet routing and etc.]]





    Example C++ Source code for your reference are Available at SampleC++Code for Assign 4

    Write a 4 page report on your design, implementation issue and results. Result should includes speed up, execution time on PC with using and with out using FPGA, and number of resources (CLB, DSP, BRAM and Reg) used in FPGA.
Lab Class timing, Venue and Rules