CS223 (Hardware Lab) Jan 2018- Apr 2018 (Instructor : A Sahu)

Timing and venue : Friday 2.00PM to 5.00PM Hardware Lab, CSE,
Group and Marks : [[ Group Structure ]] [[ Marks of Group and Individuals]]

Teaching Assistants: Pradeep Sharma (PhD), Rakesh Pandey (PhD), Manojit Ghose (PhD), Siva Kumar S (PhD), PAVAN TIWARI (MTech II) and VIRAL BHARAT SHAH (MTech I)
VHDL Tutorials: (1) CS223-HDL-Tut1.pdf, (2) CS223-HDL-Tut2.pdf, (3) CS223-HDL-Tut3.pdf, and (4) CS223-HDL-Tut4.pdf
Good HDL tutorial @ http://esd.cs.ucr.edu/labs/tutorial/
Assignments
Sl No and Demo Date Weight Part I Part II
1 (12th Jan) 10% (5+5) Circuit Design using Breadboard and ICs Circuit Design using FPGA and Xillinx Soft Assignment Statement PDF, [[Evaluation Sheets]]
2 (25th Jan) 10% (5+5) Circuit Design using Breadboard and ICs Circuit Design using FPGA and Xillinx Soft Assignment Statement PDF [[
3 (09th Feb) 12% (6+6) Circuit Design using Breadboard and ICs Circuit Design using FPGA and Xillinx Soft Assignment Statement PDF [[ ]]
4 (23rd Feb) 14% (7+7) Circuit Design using Breadboard and ICs Circuit Design using FPGA and Xillinx Soft Assignment Statement PDF [[ <]]
5 (16th Mar) 10% MFU design using FPGA and Xillnx Soft Assignment Statement PDF [[ >]]
6 (06th Apr) 12% Cache design using FPGA and Xillnx Soft Assignment Statemet PDF, Cache.cpp [[ ]]
7 (20th Apr) 12% Design intrusion detection system (IDS) using FPGA and Xillnx Soft Assignment Statement PDF, Input file [[]]
27th April Friday 20% Written Test (Date=27 April, Venue=Lecture Hall 4, Time=4PM-5PM)
These ICs are available in our HW Lab ICs-HWLAB-CS223.pdf
You can take help from TAs. All the TAs and Instructor of CS223 will be available in lab timing. You can ask TAs or Raktajit Pathak (Room CSE H101) or Bhriguraj Borah (Room CSE Server Room) about licensing and installation of ISE software. Bread board and required ICs may be issued from Hemanta Nath (Hardware Lab).

Xilinx ISE download, installation and license help is here

Grade will be based on (a) Correctness, (b) Quality of design, (c) Wire optimization, (d) Optimum number of chip used,(e) Cleanliness in design (Wire and Chips should be organized to look good), (f) Use of proper Comment/Naming/Labeling of the wires and (g) Questionnaire and explanation.

And for HDL code: the quality will be based on FPGA utilization (Synthesis Report: optimized number of LUTs, register, Minimum Clock), coding style, performance and comments
General rules:
  1. There will be 7 assignments: 4 assignments before Mid Semester and 3 after the mid semester, there will be a written examination all individual (not in a group).
  2. Weights of assignments: A1(10%)+A2(10%)+A3(12%)+A4(14%)+A5(10%)+A6(12%)+A7(12%) and Written Exam (20%)
  3. Copy of code will lead to Fail Grade to whole group: both source and destination, if you are copying from any other sources (Internet/Googling), you need to ensure that no other group copy the same from that sources :)
  4. Your source code will be checked with plagarism check software TurnitIn/MOSS. You need to submit/send the source code just after the demo or TA/Evaluator will collect the code at the time of Demo.
  5. We will issue up to three FPGA Boards (one BASYS, one ZYBO and one ATLYS) for each group for the whole semester. You need to keep the board with you for the whole semester. Based on your requirement, please issue the board from Lab in charge.
  6. Instructor and TAs will be available in Lab at Lab hours: you can clarify your doubt at Lab hours. We don't take attendance in Lab hours. It is not mandatory to stay in Lab in the Lab hours, but you need to show your demo before deadline.