CS 526: CAD for VLSI (January-May, 2018)

Assignment Details

[**Sample Input format]**
Group No.	Roll No.	Name	Research Study / Project Implementations	Project / Research Paper Allotted
1	174101010 174101017 174101036	SHUBHAM BARUA ANUJ SHARMA RODRIGUES RODNEY STEPHEN ROCKY	Research Study	Reliability Aware Real Time Scheduling Strategies for Heterogeneous Embedded Systemspapers\reliability-aware-real-time-scheduling.pdf
2	174101005 174101012	M KRISHNANANDA SINGH AJAY BANSHKAR	Research study	Soft and Hard Reliability-Aware Scheduling for Multicore Embedded Systems with Energy Harvesting papers\reliability-aware-scheduling.pdf
3	174101002 174101051 174101057 174101043	DIVYAM KUMAR LAMIYAN RONAK GOYAL AVINASH YADAV KRISHNA KUMAR	Research Study	Machine learning in VLSI CAD /EDA papers\tutorial1.pdf
4	174101032 174101040 174101042	ABHINAV ARORA ISHITA PRASITA MUKHERJEE	Research Study	Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAspapers\p5-monson.pdf
5	176101102 176101104	ALAKESH KALITA MAITHILEE LAXMANARAO PATAWAR	Research Study	High-level Synthesis for Low Power
6	176101003	DEBABRATA SENAPATI	Research Study	Multi-processor Scheduling
7	176101002 176101010 176101013	ASWATHY N S SIVAKUMAR S SUMITA MAJHI	Research Study	OpenCL and A Framework for OpenCL Task Scheduling on Heterogeneous Multicorespapers\openCLTaskScheduling.pdf
8	140102013 174101007 174101018 174101034	BEDEKAR NANDAN MILIND RAJESH KUMAR JHA SUVARIYA AMIT ASHOKBHAI SAMUJJAL DAS	Project	ISCAS89 to Verilog converter
9	174101009 174101011 174101021 174101019	SHUBHAM JAISWAL AYUSHI MATHUR AKANKSHA SINGH SACHIN KUMAR MADDHESHIYA	Project	C to CDFG Generation
10	174101008 174101029 174101039 174101046	ASHISH RAJORIYA PANKAJ KUMAR KAUSHIK KHUSHBOO TAK BHUPENDRA SAKWAR	Project	Wide-multiplier decomposition and Data path width propagation
11	174101013 174101037 174101045	ANKUR GARG VIVEK KUMAR PUNEET RAJ RAIPURIA	Project	List Scheduling
12	174101004 174101047 174101054	SORTHIYA PARTH M PRIYA BADCHARIYA VIRAL BHARAT SHAH	Project	FU and Register allocation and Binding
13	174101027 174101030 174101030 174101022	SYED ZAINUAL MD ZAKI ANWER PAMMI SAIRAM NEELKAMAL	Project	Data path and Controller Generation
14	174101006 174101015 174101035	NADAPANA ASHWANI PAKA HEMA CHANDRA KUMAR SALIHUNDAM BABY SAI SAMEERA	Project	Verilog Generation from CP-DP information

1. The Objective is to build a High-level Synthesis tool from scratch combining all Projects. The projects teams should work interacting each other.

2. Define the interface first between each project. Each team work in parallel assuming a certain input and output format

3. Take the DIFFEQ example and create the interface file for each other.

CS 526: CAD for VLSI (January-May, 2018)

Assignment Details