Chandan Karfa
CS 221: Digital Design
Announcements:
7th October 2020: Examination Schedule: Module 3: Friday 9th October 2020 9AM-10AM : syllabus: Lectures 13-16 - MCQ;
Module 4: Friday 16th October 2020 9AM-10AM Syllabus: Lectures 17-21 - Descriptive Question;
Module 5: Friday 23th October 2020 9AM-10AM: Syllabus: Lectures 1-21 - MCQ;
23rd Sept 2020: Examination of Module 2 is scheduled on 1st October 2020 during class hour (9AM-9:40AM) in MS Teams
22nd Sept 2020: Assignment 2 submission deadline is 27th September 2020.
22nd Sept 2020: Syllabus for Module 2: Verilog Minimization of switching functions (Lectures 6-12).
15th Sept 2020: Examination of Module 1 is scheduled on 21st September 2020 during class hour in Moodle platform.
15th Sept 2020: Assignment for module 1: There will be Live Assignment submission on Thursday for Module 1. You have to solve the assignment within the class hour and submit within class hour in Moodle.
You need to write your answers in your copy and submit the scan copy in Moodle. It is time based submission. So, people who submit early will get extra credit. Check the MS teams course page for detail.
15th Sept 2020: Syllabus for Module 1: Topic covered till 11th September 2020.
I am posting all updates in MS Teams page. Do visit the MS Teams course page regularly.
9th Sept 2020: Online Interaction Session is scheduled on every Friday during 9AM-10AM in MS Teams. Join using the link shared in Teams Grp_CS221: Digital Design 2020.
7th Sept 2020: I am reguarly posting youtube links of the video lectures in MS Teams Group “Grp_CS221: Digital Design 2020”.
7th Sept 2020: If you have any doubts in any part of the lecture, post your questions in MS Teams Group “Grp_CS221: Digital Design 2020”.
I will answer them there or during online/live discussion session. Every week, there will one live session to discuss your queries in MS teams group.
6th Sept 2020: Online examination and Assignment submission will be done using Moodle. All of you must register for the course
“CS221: Digital Design 2020” in Moodle using the PIN sent over email.
Welcome to CS 577 Course page
Instructors
Class Timing and Venue:
Monday: 10AM-11AM, Thursday: 9AM-10AM, Friday: 9AM-10AM, and selected Saturdays
Venue: Youtube, Moodle, MS Teams
TAs with their Responsibilities:
Debabrata Senapati - debab176101003@iitg.ac.in – Video Upload, plagiarism checking, overall management.
Priyanka Panigrahi - priya176101006@iitg.ac.in – Assignment-5 Evaluation, Module 5 student interaction
Jayprakash Patidar - jpatidar@iitg.ac.in – Assignment-1 Evaluation, Module 1 student interaction
Rupak Gupta - rgupta@iitg.ac.in – Assignment-4 Evaluation, Module 4 student interaction
Arshdeep Kaur - akaur@iitg.ac.in – Assignment-3 Evaluation, Module 3 student interaction
Abhay Chandra Sonkar - achandra@iitg.ac.in – Assignment-2 Evaluation, Module 3 student interaction
Syllabus:
Review of Boolean algebra and logic minimisation;
Design of combinational logic blocks (MUX, DeMUX, encoder, decoder, adders, multipliers, etc.);
Design using combinational logic blocks;
Sequential circuit design: flip-flops, FSM, registers, counters, state tables and diagrams, state minimization, excitation functions of memory elements,
synthesis of synchronous sequential circuits; representation and synthesis using ASM charts;
Specification and synthesis of asynchronous sequential machines;
Basics of FPGA architecture;
Progamming using HDLs (Verilog).
Text Book:
[Mano] M. M. Mano and M. D. Ciletti, Digital Design, 5th Ed., Pearson Education.
[Kohavi] Z. Kohavi and N. Jha, Switching and Finite Automata Theory, 3rd Ed., Cambridge University Press, 2010.
References:
[Palnitkar] S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis,Pearson, 2nd Ed, 2003.
[Vahid] F. Vahid, Digital Design, 1st Ed., Wiley India, 2011.
Grade Calculation
Classes
Lecture No | Date | Topic | Resources |
1 | 4th Sept 2020 | Introduction to Digital Logic | |
2. | 5th Sept 2020 | Switching_Algebra | Kohavi: Ch3 |
3. | 7th Sept 2020 | Number Systems | Kohavi: Ch 1 |
4. | 10th Sept 2020 | Binary Codes | Kohavi: Ch 1 |
5. | 11th Sept 2020 | Error Detection Correction Codes | Kohavi: Ch 1 |
6. | 14th Sept 2020 | Introduction to Verilog | Palnitkar |
7. | 17th Sept 2020 | Verilog: FSM Modelling | Palnitkar |
8. | 18th Sept 2020 | Verilog: Design using Verilog | Palnitkar |
9. | 18th Sept 2020 | Verilog: Writing Testbench | Palnitkar |
10. | 21st Sept 2020 | Minimization of switching functions | Kohavi: Ch 4 |
11. | 24th Sept 2020 | Quine McClusky Method | Kohavi: Ch 4 |
12. | 25th Sept 2020 | Heuristic based minimization of switching functions | Kohavi: Ch 4 |
13. | 26th Sept 2020 | Combinational Logic Design (code conversion, parity generator, Comparator, Multiplexer) | Kohavi: Ch 5, Mano: Ch 4 |
14. | 28th Sept 2020 | Combinational Logic Design (Encoder, Decoder) | Kohavi: Ch 5, Mano: Ch 4 |
15. | 1st October 2020 | Combinational Logic Design (Ripple Carry Adder and Carry Look ahead adder) | Kohavi: Ch 5, Mano: Ch 4 |
16. | 3rd October | Combinational Logic Design (Adder/Subtractor, BCD Adder, Multiplier) | Mano: Ch 4 |
17. | 5th October | Implementation with NAND, NOR Gate | Mano: Ch 4 |
18. | 8th October | CMOS Transistors and Gates | Kohavi: Ch 5 |
19. | 9th October | Multi-level logic minimization | Kohavi: Ch 6 |
20. | 12th October | Multi-level logic minimization | Kohavi: Ch 6 |
21. | 15th October | Multi-level logic minimization | Kohavi: Ch 6 |
22-40 | | Lectures taken by Dr. A. Sahu and Dr. S. Bhattacharjee |
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Examination Schedule
Exam No | Date | Topic | Mode |
1 | 21st September | Lectures 1-5 | Descriptive - time bound |
2 | 1st October | Lectures 6-12 | Descriptive |
3 | 9th October | Lectures 13-16 | MCQ |
4 | 16th October | Lectures 17-21 | Descriptive |
5 | 23th October | Lectures 1-21 | MCQ |
6-10 | | Taken by Dr. Sahu and Dr. Bhattacharjee |
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Assignment Schedule
Assignment No | Deadline |
1 | 15th September 2020 |
2 | 27th September 2020 |
3 | 10th October 2020 |
4 | 17th October 2020 |
5-9 | Taken by Dr. Sahu and Dr. Bhattacharjee
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