Chandan Karfa

CS221: Digital Design

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Feebback on Course Instructor:

Instructors

• Dr. Chandan Karfa (till Mid-Semester)

• Prof. Hemangee Kapoor (post Mid-Semester)

Class Timing and Venue:

• Monday: 10AM-11AM, Thursday: 9AM-10AM, Friday: 9AM-10AM.

• Venue: L4.

TAs with their Responsibilities:

• Debabrata Senapati - debab176101003@iitg.ac.in

• Priyanka Panigrahi - priya176101006@iitg.ac.in

• Nilotpola Sarma - s.nilotpola@iitg.ac.in

• Prosenjit Biswas - prosenjit.biswas@iitg.ac.in

• Rittick Mondal - rittickmondal@iitg.ac.in

• Divyanshu Nauni - divyanshu_nauni@iitg.ac.in

Syllabus:

• Review of Boolean algebra and logic minimisation;

• Design of combinational logic blocks (MUX, DeMUX, encoder, decoder, adders, multipliers, etc.);

• Design using combinational logic blocks;

• Sequential circuit design: flip-flops, FSM, registers, counters, state tables and diagrams, state minimization, excitation functions of memory elements, synthesis of synchronous sequential circuits; representation and synthesis using ASM charts;

• Specification and synthesis of asynchronous sequential machines;

• Basics of FPGA architecture;

• Progamming using HDLs (Verilog).

Text Book:

• [Mano] M. M. Mano and M. D. Ciletti, Digital Design, 5th Ed., Pearson Education.

• [Kohavi] Z. Kohavi and N. Jha, Switching and Finite Automata Theory, 3rd Ed., Cambridge University Press, 2010.

References:

• [Palnitkar] S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis,Pearson, 2nd Ed, 2003.

• [Vahid] F. Vahid, Digital Design, 1st Ed., Wiley India, 2011.

Grade Calculation

• Quiz: 20%.

• Mid-Sem Examinations: 40%.

• End-Sem Examinations: 40%

Classes (Last Year)