Chandan Karfa

CS 577: C-Based VLSI Design

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Instructors

• Dr. Chandan Karfa

Cource Overview

• High-level Synthesis (HLS) is the process of generating effecient hardware at register transfer level (RTL) from the input C-code (high-level code). HLS is an active domain of research in recent times in the domain of electronic Design Automation (EDA) of VLSI. This course will help the students to understand

  • the overall C to RTL synthesis flow,

  • how a C-code will be converted to its equivalent hardware,

  • how to write C-code for efficient hardware generation,

  • how the common software compiler optimizations can help to improve the circuit performance.

  • Hardware Acceleration of Machine Learning Algorithm

  • Secure Hardware generation using HLS

  • Equivalence checking between C and RTL.

  • The overall EDA tool flow.

• This course will help the students to take up research in the domain of HLS. Also, this course will help the students to become proficient for EDA industries.

• Pre-requisites: (1) Basic knowledge of digital circuits (2) Basic knowledge of Data structures and algorithms

Class Timing and Venue:

• Slot G in timetable for Open Electives

• Wednesday: 12PM-1PM, Thursday: 12PM-1PM, Friday: 12AM-1PM

• Venue: MS Teams

• Mode of Lecture: Live session in the class hour. Few live interaction sessions to clear doubts/discussions.

Teaching Assistants:

• Debabrata Senapati - debab176101003@iitg.ac.in

• Priyanka Panigrahi - priya176101006@iitg.ac.in

• Nilotpola Sarma - s.nilotpola@iitg.ac.in

• Modammed Abderahman - ma.adem@iitg.ac.in

• Abhik Paul apaul@iitg.ac.in

• Mukul Chaturvedi - mchaturvedi@iitg.ac.in

• Navjot Singh - navjot_singh@iitg.ac.in

Syllabus:

• Electronic Design Automation flow: Overview of high-level synthesis, logic synthesis and physical synthesis;

• High-level Synthesis (HLS) Fundamentals: Overview HLS flow, Scheduling Techniques, Resource sharing and Binding Techniques, Datapath and Controller Generation Techniques;

• Impact of C-coding style on Hardware: Data types, Synthesis of Loops, Functions, RAM, ROM, Shift register inference from arrays;

• Impact of Compiler Optimization in HLS results: Impact of Compiler optimizations like copy propagation, constant propagation, common sub-expression elimination, loop transformations, code motions, etc., in HLS results;

• HLS for Security: RTL Locking, Logic Locking, Attack and Defense techniques;

• RTL Optimizations Techniques: Various optimization techniques to improve latency, area and power in C-based VLSI designs;

• High-level Synthesis Verification: BDD, Simulation based verification, Equivalence checking between C and RTL;

• Hardware acceleration of Machine Learning Algorithms

• Domain Specific High-level Synthesis

Text Book:

• [Micheli] G. De Micheli. Synthesis and optimization of digital circuits, McGraw Hill, India Edition, 2003.

• [Elliot] J. P. Elliot, Understanding Behavioural Synthesis: A Practical guide to High-level Synthesis, Springer, 2nd edition, 2000

• [Kilts] Steve Kilts, Advanced FPGA Design, Wiley, 2007.

• [Parhi] K. Parhi: VLSI Digital Signal Processing Systems: Design and Implementation, Jan 1999, Wiley.

• [Huth] M. Huth and M. Ryan, Logic in Computer Science: Modelling and Reasoning about Systems, 2nd Ed, Cambridge University Press, 2004.

• Various Research Papers.

References:

• [Gajski] D. D. Gajski, N. D. Dutt, A.C.-H. Wu and S.Y.-L. Lin, High-Level Synthesis: Introduction to Chip and System Design, Springer, 1st edition, 1992

• [BlueBook] Mike Fingeroff, High-Level Synthesis Blue Book, Mentor Graphics Corporation, 2010.

• Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer, Parallel Programming for FPGAs, 2018.

• Philippe Coussy and Adam Morawiec, High-level Synthesis from Algorithm to Digital Circuit, Springer, 2008

• David. C. Ku and G. De Micheli, High-level Syntehsis of ASICs Under Timing and Synchronization Constraints, Kluwer Academic Publishers, 1992.

• T. F. Melham, Higher Order Logic and Hardware Verification, Cambridge University Press, 1993.

Grade Calculation

• Quizzes: 20% - Two quizzes each carries 10% of total marks.

• MidSem: 15%

• End Sem: 25%

• Project: 20%. A group of 4/5 students to be assigned to a project.

• Class participation: 10%. There will be short pop quizzes during most of the live sessions to cover key topics discussed in the current or previous lecture. Your attendance in the class will also be monitored.

• Student-led discussion: 10%. A group of 4/5 students to be assigned to a topic (The group will be same as project group). There will be a student-led presentation for each group on the assigned research topics.

Classes

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