Ongoing Ph.D. Students

Nilotpola Sarma Nilotpola Sarma

January 2021-

Area: Design Autiomation and Verificaton of Masking

Email: s.nilotpola@iitg.ac.in

Praveen Karmakar Praveen Karmakar

July 2022-

Area: Logic Locking

Email: pkarmakar@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

Akash Lal Dutta Akash Lal Dutta

July 2022-

Area: ML for Logic Synthesis

Email: akash@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

Bhabesh Mali Bhabesh Mali

July 2023-

Area: ML/LLM for EDA

Email: m.bhabesh@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

E Bhawani Eswar Reddy E Bhawani Eswar Reddy

July 2023-

Area: Acclerator Design and Security Analysis of ML

Email: r.eddula@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

Innocent Mochahari Innocent Dengkhw Mochahari

July 2024-

Area: ML for Physical Synthesis

Email: innocent@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

Nishant Kumar Nishant Kumar

July 2025-

Area: Formal Verification

Email: nishantk@iitg.ac.in

(Joint supervision with Dr. Sukanta Bhattacharjee)

Graduated Ph.D. Students

Priyanka Panigrahi Dr. Priyanka Panigrahi

July 2017 – November 2023

Area: Security Verification of Compiler Optimizations: An Information Flow Perspective

Email: priya176101006@iitg.ac.in

Next Position: Assistant Professor, IIT Dhanbad

Debabrata Senapati Dr. Debabrata Senapati

July 2017 – June 2023

Thesis: Efficient Techniques for Scheduling DAG Applications in Distributed Environments

Email: debab176101003@iitg.ac.in

Next Position: Assistant Professor, SRM University

(Joint supervision with Dr. Arnab Sarkar)

Mohammed Aderehman Adem Dr. Mohammed Aderehman Adem

January 2018 – October 2022

Thesis: Reverse-Engineering of High-level Synthesis and Its Applications

Email: ma.adem@iitg.ac.in

Next Position: Faculty at Defence Engineering College, Ethiopia

Surajit Das Dr. Surajit Das

August 2016 – May 2022

Thesis: Formal Modeling of Network-on-Chip and its Applications in Starvation and Deadlock Detection and in Developing Deadlock Free Routing Algorithms

Email: d.surajit@iitg.ac.in

Next Position: Assistant Professor, National Forensic Sciences University, Delhi

(Joint supervision with Dr. Santosh Biswas)

Ramanuj Chouksey Dr. Ramanuj Chouksey

August 2016 – August 2020

Thesis: Formal Verification and Security Analysis of High-level Synthesis

Email: r.chouksey@iitg.ac.in

Next Position: Lead Engineer at Cadence

Ongoing M.Tech. Students

Mani Deep G Mani Deep G

2024 – 2026

Thesis: Hardware Accelerator for Hybrid Transformer-based Underwater Object Detection

Shipon Nandy Shipon Nandy

2024 – 2026

Thesis: A Reinforcement Learning Guided Scheduling in High-Level Synthesis

Tapish Patidar Tapish Patidar

2024 – 2026

Thesis: Design Space Exploration of Gadget-Based Masked Cryptographic Hardware

Tellabiyyam Abhilash Tellabiyyam Abhilash

2024 – 2026

Thesis: Physical Aware Logic Restructuring for Timing Improvement

Naman Baveja Naman Baveja

2024 – 2026

Thesis: MCTS-based Logic Restructuring for Timing Closure in Physical Synthesis

Chirag Gajbhiye Chirag Gajbhiye

2024 – 2026

Thesis: Machine Learning Guided Technology Mapping in the ABC Logic Synthesis Framework

Ongoing B.Tech. Students

Aditya Kumar Aditya Kumar

2022 – 2026

Thesis: ML for Logic Synthesis

Brajesh Muwel Brajesh Muwel

2022 – 2026

Area: RTL Power Prediction

Kotha Hitesh Kotha Hitesh

2022 – 2026

Thesis: Biochip (guided by Dr. Sukanta)

Mohd Faiz Mohd Faiz

2022 – 2026

Thesis: Physical Aware Logic Syntesis

Patel Dhyey Sanjaykumar Patel Dhyey Sanjaykumar

2022 – 2026

Area: Netlist to RTL Reverse Engineering

Shashwat Shankar Shashwat Shankar

2022 – 2026

Thesis: LLM for EDA

Shobhit Gupta Shobhit Gupta

2022 – 2026

Thesis: RL for Scheduling in HLS

Shubhranshu Pandey Shubhranshu Pandey

2022 – 2026

Thesis: LLM for EDA

Vidhi Arora Vidhi Arora

2022 – 2026

Thesis: LLM based Verification Assertion Generation

Vikrant Vikrant

2022 – 2026

Thesis: Biochip (guided by Dr. Sukanta)

Parv Aggarwal Parv Aggarwal

2022 – 2026

Thesis: Physical Aware Logic Syntesis

Many of the M.Tech. and B.Tech. students are co-guided with Dr. Sukanta Bhattacharjee.

Graduated M.Tech. Students

Harshita Rakesh Mishra Harshita Rakesh Mishra

2023 – 2025

Thesis: Protecting ML models from Physical Side Channel Attacks via Masking

Navdeep Patel Navdeep Patel

2023 – 2025

Thesis: Power Side-Channel Secure Register Transfer Level Design using Ad-hoc Techniques

Mukesh Barpete Mukesh Barpete

2023 – 2025

Thesis: BDD Based Attack on Logic Locking

Sunny Priyadarshi Sunny Priyadarshi

2023 – 2025

Thesis: RTL Information Leakage Analysis and its Application in Analysis of High-level Synthesis Security

Nupur Brahmanya Nupur Brahmanya

2023 – 2025

Thesis: Design Space Exploration of Gadget-based Masked Hardware

Manish Joshi Manish Joshi

2023 – 2025

Thesis: Efficient High-Level Synthesis of Post Quantum Cryptography Algorithms

Vaishali Chaudhari Vaishali Chaudhari

2022 – 2024

Thesis: Formal Verification of PSCA Security of High Level Synthesis Generated Cryptographic Design

Anuj Singh Thakur Anuj Singh Thakur

2022 – 2024

Thesis: Power Side-Channel Secure Register Transfer Level Design

Karthik Maddala Karthik Maddala

2022 – 2024

Thesis: Exploring Advanced Verification Techniques: From Security Verification of LLVM, Hardware Fuzzing and Automated Assertion Generation

Debarpan Jana Debarpan Jana (with Dr. Sukanta Bhattacharjee)

2022 – 2024

Thesis: An SMT based Model Extraction Attack on Neural Networks

Ayush Mandloi Ayush Mandloi (with Dr. Sukanta Bhattacharjee)

2022 – 2024

Thesis: An Oracle Guided Attack on State Space Obfuscation Technique

Jatin Gupta Jatin Gupta (Part time student)

2021 – 2024

Thesis: Statistical Attack on Logic Locked Designs with Dishonest Oracle

Divyanshu Nauni Divyanshu Nauni

2021 – 2023

Thesis: Logic Locking: Analysing the Area and Latency Overhead of Locked Designs

Prosenjit Biswas Prosenjit Biswas

2021 – 2023

Thesis: C to RTL Equivalence Checking

Rittick Mondal Rittick Mondal

2021 – 2023

Thesis: Scalable SMT Attack on Higher Level Locking

Shubham Sachan Shubham Sachan (Jointly with Dr. Prithwijit Guha)

2021 – 2023

Thesis: Predicting Robustness of Logic Locking

Subham Das Subham Das (Part time student)

2020 – 2023

Thesis: Attacks on locked Combinational and Sequential circuits

Mukul Chaturvedi Mukul Chaturvedi

2020 – 2022

Thesis: Verification of Dataflow Optimization in Array-Intensive Programs

Abhik Paul Abhik Paul

2020 – 2022

Thesis: Information Leakage Analysis of Compiler Optimizations

Navjot Singh Navjot Singh

2020 – 2022

Broad Area: Logic Encryption at Higher Abstraction Level

Rupak Gupta Rupak Gupta

2019 – 2021

Thesis: Hardware Trojan Detection in High-level Synthesis Generated RTLs

Jayprakash Patidar Jayprakash Patidar

2019 – 2021

Thesis: An RTL-to-C Reverse Engineering based Fast Simulation Framework for High-level Synthesis

Arshdeep Kaur Arshdeep Kaur

2019 – 2021

Thesis: A Statistical Approach to Measure Robustness of Gate-Level Logic Locking

Gagan Gayari Gagan Gayari (Jointly with Dr. Prithwijit Guha)

2019 – 2021

Thesis: Genetic Algorithm based Attack on Register Transfer Level Locking

Jay Oza Jay Oza

2018 – 2020

Thesis: A Fast Simulation Framework for High-level Synthesis

Yom Nigam Yom Nigam

2018 – 2020

Thesis: Register Transfer Level Logic Obfuscation

Samujjal Das Samujjal Das

2017 – 2019

Thesis: Property Verification in Business Process Models embedded with SBVR-based Business Rules

Sachin Kumar Maddheshiya Sachin Kumar Maddheshiya

2017 – 2019

Thesis: Formal Verification of Testability Transformations

Suvariya Amit Ashokbhai Suvariya Amit Ashokbhai

2017 – 2019

Thesis: Deadlock and Livelock Detection in NoC using Generic Communicating Finite State Machine

(Joint supervision with Dr. Santosh Biswas)

Rajesh Kumar Jha Rajesh Kumar Jha

2017 – 2017

Thesis: Register Manipulation using Automatic Register Balancing

(Joint supervision with Dr. Santosh Biswas)

Pankaj Kumar Kalita Pankaj Kumar Kalita

2016 – 2018

Thesis: Inverse Operation Detection and Counter Example Generation during Path Based Equivalence Checking

Pavan Ganesh Jeereddy Pavan Ganesh Jeereddy

2016 – 2018

Thesis: NoC Verification: Deadlock Detection Using Bottom Up Approach

(Joint supervision with Dr. Santosh Biswas)

Ajinkya Sanjay Mankar Ajinkya Sanjay Mankar

2016 – 2018

Thesis: A Top-Down Approach for Deadlock Detection in NoC Using Communicating Finite State Machine

(Joint supervision with Dr. Santosh Biswas)

Graduated B.Tech. Students

Himanshi Gautam Himanshi Gautam

2021 – 2025

Thesis: ML for EDA

Yash Raj Singh Yash Raj Singh

2021 – 2025

Area: Attack on Sequential Logic Locking

Satyarth Gupta Satyarth Gupta

2021 – 2025

Thesis: ML for Logic Locking

Ankita Kanoji Ankita Kanoji

2021 – 2025

Thesis: ML based Simulation Acceleration

Kshitij Maurya Kshitij Maurya

2021 – 2025

Thesis: Logic Synthesis

Bussa Sai Santhosh Bussa Sai Santhosh

2021 – 2025

Area: ML for EDA

Bhogi Sai Sathwik Bhogi Sai Sathwik

2021 – 2025

Thesis: ML for EDA

Meghna Battu Meghna Battu

2021 – 2025

Thesis: EDA

Harshit Seksaria Harshit Seksaria

2021 – 2025

Thesis: Logic Synthesis

B Vijesh R Bhat B Vijesh R Bhat

2021 – 2025

Thesis: Security Verification

Dhruv Patel Dhruv Patel

2021 – 2025

Thesis: Security Verification

G. Sai Ram Moham G. Sai Ram Moham

2020 – 2024

Thesis: Protection Against Scan-Chain-Based Model Extraction Attacks (Jointly with Dhruv)

Dhruv Shah Dhruv Shah

2020 – 2024

Area: Security of ML Model

Sujeet Narayan Kamble Sujeet Narayan Kamble

2020 – 2024

Thesis: Power Side Channel Secure RTL Design

Chandrabhushan Reddy Chandrabhushan Reddy

2020 – 2024

Thesis: ML Guided Cut Choices for ASIC Technology Mapping (Jointly with Harsh)

Harshwardhan Bhakkad Harshwardhan Bhakkad

2020 – 2024

Area: ML for EDA

Anmoldeep Singh Anmoldeep Singh

2020 – 2024

Thesis: Attacks on Combinational and EFPGA Logic Locking (Jointly with Kartik)

Kartik Sharma Kartik Sharma

2020 – 2024

Area: Logic Locking

M. Samson M. Samson

2020 – 2024

Thesis: Identifying Information Leakage in RTL Design

Hetang Patel Hetang Patel

2020 – 2024

Thesis: Speedup of RTL Simulation Using Machine Learning Techniques

Tanay Maheshwari Tanay Maheshwari

2019 – 2023

Thesis: Counter Example Generation for Insecure Transformation of Compiler Optimizations

Vignesh Ravichandra Rao Vignesh Ravichandra Rao

2019 – 2023

Thesis: Power Side Channel Secure RTL Design

Marpina Bharani Marpina Bharani

2019 – 2023

Thesis: Scalable Attack on Combinational Circuits

Ritik Kumar Ritik Kumar

2019 – 2023

Thesis: High Level Synthesis and Optimization of ML Models

Bodavula Teja Sai Srikar Bodavula Teja Sai Srikar

2019 – 2023

Thesis: Translation Validation of High Level Synthesis

Saaketh Gunti Saaketh Gunti

2019 – 2023

Thesis: SAT Based Attacks on Machine Learning Models

Rahul Reddy Peddaiahgari Rahul Reddy Peddaiahgari

2019 – 2023

Thesis: Predicting Outputs of RTL Circuits Using Machine Learning

Naresh Bharasagar Naresh Bharasagar

2018 – 2022

Thesis: Formal Verification of Security Countermeasures Against Power Side-Channel Attacks

Pooja Gajendra Bhagat Pooja Gajendra Bhagat

2018 – 2022

Thesis: Security-Aware DAG Scheduler for Heterogeneous Distributed Systems

Param Aryan Singh Param Aryan Singh

2018 – 2022

Thesis: Hardware Security against IP Theft

Kousik Rajesh Kousik Rajesh

2018 – 2022

Thesis: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems

Dristiron Saikia Dristiron Saikia

2018 – 2022

Thesis: Security Analysis of C/C++ Programs

Shivam Kumar Agarwal Shivam Kumar Agarwal

2018 – 2022

Broad Area: Formal Verification Of Security Measures Against Timing Side-Channel Attacks

Soumik Paul Soumik Paul

2017 – 2021

Broad Area: Hardware Trojan Detection in Post-silicon Validation

Vemuri Sahithya Vemuri Sahithya

2017 – 2021

Broad Area: Analysis of Information Leakage in LLVM Compiler

T. Rakesh Reddy T. Rakesh Reddy

2017 – 2021

Broad Area: Data-driven Equivalence Checking

Rajanala Harshavardhan Reddy Rajanala Harshavardhan Reddy

2017 – 2021

Broad Area: Logic Locking

Rashi Singh Rashi Singh (Jointly with Dr. S. Bhattacharjee)

2017 – 2021

Broad Area: Compiler Security

Aadil Hoda Aadil Hoda

2016 – 2020

Broad Area: Logic Locking

Shimona Verma Shimona Verma

2016 – 2020

Broad Area: Hardware Trojan Detection

Abhishek Bhardwaj Abhishek Bhardwaj

2016 – 2020

Broad Area: Equivalence Checking of Programs

Abhisheh Suryavanshi Abhisheh Suryavanshi

2016 – 2020

Broad Area: HLS Obfuscation

Harshit Bansal Harshit Bansal

2015 – 2019

Broad Area: Verification of Deep Neural Networks

Mayank Yadav Mayank Yadav

2015 – 2019

Broad Area: Verification of Deep Neural Networks

Ayush Soni Ayush Soni

2015 – 2019

Broad Area: Deep Steganography

Ayush Singh Ayush Singh

2015 – 2019

Broad Area: Verification of Database Driven Applications

Manish Kumar Regar Manish Kumar Regar

2014 – 2018

Broad Area: Bottom-up Equivalence Checking

Shah Het Jageshkumar Shah Het Jageshkumar

2014 – 2018

Broad Area: High-level Synthesis

Datir Vivek Prabhakar Datir Vivek Prabhakar

2014 – 2018

Broad Area: High-level Synthesis

Abhisheh Kumar Abhisheh Kumar (working with Dr. Deepak Garg, MPI)

2014 – 2018

Broad Area: Type systems and secure compilation of WebAssembly

Jayesh Mathur Jayesh Mathur (Jointly with Dr. Santosh Biswas)

2014 – 2018

Broad Area: Loop Invariant Generation

Ravi Kumar Ravi Kumar

2013 – 2017

Area: Program Equivalence using CVC4

Jitendra Choudhary Jitendra Choudhary

2013 – 2017

Area: Program Equivalence using CVC4 (Joint project with Ravi Kumar)

Siddharth Kumar Siddharth Kumar

2013 – 2017

Area: Verification of Testability Transformations

Pallavi Yellamelli Pallavi Yellamelli (Jointly with Dr. Sharmistha Banerjee, DoD)

2013 – 2017

Area: Design and Development of a Material Selection Software