Syllabus:

Nano-devices: physics and modelling (EE 511)

L-T-P-C : 3-0-0-6
Course Contents:

Wave-particle duality, Schrödinger wave equation; electrons in solids and low-dimensional structures, k-space, Brillouin zone; basics of semiconductor physics, review of p-n, Schottky junction theory, and BJT; MOS capacitor- effects of real surfaces; threshold voltages MOSFET- threshold based models, output and transfer characteristics. Short channel and narrow width effects, subthreshold characteristics and quantum mechanical effects. Surface potential and charge-based models, principles of MOSFET scaling. Nano-scale devices- physics and modelling of SOI, double gate MOSFETs, FinFETs, and GAA MOSFETs around, SOI

Texts/References:

1. S. A. Neamen and D. Biswas, Semiconductor Physics and Devices, 4^th Edition, TMH, 2012.
2. P. Bhattacharya, Semiconductor Optoelectronics Devices, 2^th Edition, PHI, 2017.
3. V. V. Mitin, V. A. Kochelap, M. A. Stroscio, Introduction to Nanoelectronics Science, Nanotechnology, Engineering, and Applications, Cambridge University Press, 2008.
4. S. Datta, Quantum Transport: Atom to Transistor, Cambridge University Press, 2005.
5. S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 4^th Ed., Wiley India, 2021.
6. Y. Tsividis, Operation and Modeling of the MOS transistor, 4^th Ed., TMH, 2010.

Nanoelectronics Fabrication Technology (EE 513)

L-T-P-C : 2-0-4-8
Course Contents:

Crystal growth and defects, clean room technology, wafer cleaning, thermal oxidation; lithography techniques, wet and dry etching; thin film deposition technique, physical and chemical vapour deposition techniques; epitaxy, doping, diffusion, ion implantation; metallization; process integration; passive components, bipolar, CMOS and MEMS technology; IC, manufacturing; electrical testing, packaging, yield; future trends and challenges, challenges for integration, system on chip. Laboratory component will include identifying different wafers and cleaning procedures of these wafers, oxidation of silicon wafer, photolithography, wet etching, metallization, thin film deposition by physical vapor deposition technique (beyond metallization), thin film deposition by chemical vapor deposition technique, electrical characterization, wire bonding.

Texts/References:

1. R. C. Jaeger, Introduction to Microelectronic Fabrication, Vol. 5 (Modular Series on Solid State Devices), 2^nd Edition, Prentice Hall, 2001.
2. P. V. Zant, Microchip Fabrication: A Practical Guide to Semiconductor Processing, 6^th Edition, McGraw Hill, 2014
3. J. D. Plummer, M. D. Deal and P. B. Griffin, Silicon VLSI Technology, Fundamentals, Practice and Modeling, Pearson education, 2009.
4. G. S. May and S. M. Sze, Fundamentals of Semiconductor Fabrication, Wiley India, 2004.
5. S. M. Sze, Semiconductor Devices: Physics and Technology, 2^nd Edn., Wiley India, 2011.
6. M. J. Madou, Fundamentals of Microfabrication and Nanotechnology, 3^rd Edition, CRC Press, 2011.
7. H. Geng, Semiconductor Manufacturing Handbook, 2^nd Edition, McGraw Hill, 2017

Digital IC design (EE 514)

L-T-P-C : 3-0-0-6
Course Contents:

CMOS logic, inverter, buffer, NAND, NOR, XOR, compound gates, pass transistors and transmission gates ; power and power management methods; CMOS inverter, latch-up, robustness, dynamic performance, regenerative property; delay, RC delay model, linear delay models, logical effort, timing analysis delay model; combinational circuit design, circuit families, SoI circuits, subthreshold circuits; MOSFET scaling; dynamic CMOS design, steady-state behaviour, noise, charge sharing, cascading, domino logic, np-CMOS logic, clocking schemes; sequential circuit design: static circuits, latches and flip-flops, sequencing methodology, synchronizers, pipelining; low power circuit design.

Texts/References:

1. J. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits, A Design Perspective, 2^nd Edition, Pearson Education, 2017.
2. N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4^th Edition, Pearson, 2015.
3. N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design - a System Perspective, 2^nd Edition, Pearson Education Asia, 2002.
4. R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, IEEE Press, 1997.

Digital IC design lab (EE 518)

L-T-P-C : 0-0-4-8
Course Contents:

Basic Design Flow using Open source softwares, Pre-Layout and Post-Layout Validation; Concepts of Physical Design; Floor planning, Placement and Routing; Introduction to HDL, Verilog, Design Synthesis; Lab Project.

Texts/References:

1. M. H. Rashid, Introduction to PSpice Using OrCAD for Circuits and Electronics, 3^rd Edition, Prentice-Hall India, 2006.
2. Mentor Graphics, Synopsys, Cadence and Xilinx Vivado EDA Tools Manuals.

Foundation of VLSI architectures (EE 515)

L-T-P-C : 3-0-0-6
Course Contents:

Introduction to VLSI design flow, importance of VLSI architectures and its optimization; high throughput, low power and low area architectural optimization techniques: Pipelining, parallel processing, unfolding, retiming, folding; application of these techniques to realize signal processing, machine learning and communication systems. Specialized VLSI architectures: systolic array, CORDIC, distributed arithmetic, canonical signed digit arithmetic and redundant arithmetic; application of these VLSI architectural designs to implement signal processing and communication systems.

Texts/References:

1. U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Array, Springer, 2014.
2. K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, Wiley, 2007.
3. M. J. S. Simth, Application Specific Integrated Circuits, Pearson Education, 2011.

System Hardware Design (EE 516)

L-T-P-C : 2-0-4-8
Course Contents:

Design methodologies, flow, partitioning, logic design, verification; packaging and testing; finite state machines, logic synthesis techniques, design optimization; interconnect modelling, logical efforts with wires; variability, reliability, statistical analysis of variability, variation-tolerant design; data path subsystems; array subsystems; chip power distribution network design ; clock distribution; I/O design; high speed interconnects; logic verification; DFT; Lab exercises based on the design of IPs using FPGA in Verilog/VHDL and their verification.

Texts/References:

1. N.Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4^th Edition, Pearson, 2015.
2. J. Rabaey, Digital Integrated Circuits, A Design Perspective, 2^nd Edition, Pearson Education, 2016.
3. D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 6^th Edition, Morgan Kaufmann Publishers, Inc, 2020.
4. G. De. Micheli, Synthesis and Optimisation of Digital Circuits, Tata McGraw-Hill, 2004.
5. W. Wolf, High-Performance Embedded Computing: Architectures, Applications, and Methodologies, Morgan Kaufmann, 2010.

Analog VLSI Lab (EE 517)

L-T-P-C : 0-0-4-8
Course Contents:

NMOS and PMOS characteristics; common source amplifiers; layout of resistors, capacitors, transistors; differential amplifier; cascode amplifier; current mirror; push pull CS amplifier; negative feedback amplifier; multistage amplifiers; operational amplifiers and comparators.

Texts/References:

1. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2^nd edition, 2017.
2. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 3^rd Edition, Oxford University Press, 2016.
3. D. A. Johns and K. Martin, Analog Integrated Circuit Design, Wiley Student Edition, 2002.
4. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4^th Edition, Wiley Student Edition, 2001.