With the end of Moore's law and Dennard scaling, general-purpose computer architectures are suffering the so called "Turing tariff" that refers to the cost of performing functions using general-purpose hardware. The term is based on the idea the theoretical machine proposed by Alan Turing could perform any function, but not necessarily efficiently. Thus, future opportunities in computer architectures are evolving toward the concept of domain-specific architectures (DSAs). A DSA, also called accelerator, is tailored to a specific problem domain and offers significant performance (and efficiency) gains for that domain. An accelerator pays a lower Turing tariff for its intended functions because operations that are implicit in the module's circuitry need to be explicitly defined in software when run on a general-purpose processor. Examples of DSAs include graphics processing units, neural network processors used for deep learning, and processors for software-defined networks.

In recent years we are witnessing the explosion of tasks previously implemented by handcrafted programming but now more efficiently and easily implemented by means of artificial intelligence (AI) techniques. Among the different AI techniques, Deep Neural Networks (DNNs) find application in many different areas, including self-driving cars, natural language processing, entertainment, visual recognition, fraud detection, healthcare, and many others. The expanding AI market along with the high computation capabilities demanded for the execution of DNN inferences (involving tens of GOps per inference) is boosting the research toward efficient DNN DSAs. The workshop provides a general overview on DSAs and focuses on DSAs for accelerating DNN inferences covering different aspects, including, data-flow techniques, compression techniques, memory and communication related issues.

• Inefficiency in General Purpose architectures
• Domain Specific Architectures
• Source of acceleration
• Communication issues
• Basics on Deep Neural Networks
• Kernel computation
• Data-flow techniques
• Energy-efficient data-flow techniques
• DNN accelerators architectures: Eyeriss, Simba
• Improving performance and energy through model compression

Dr. MAURIZIO PALESI Associate Professor Department of Computer Engineering University of Catania, Italy.

Dr. Maurizio Palesi is an Associate Professor in Computer Engineering at University of Catania, Italy. His research activity is focused in the area of embedded systems with particular emphasis on single-chip implementations based on the network-on-chip design paradigm. He has served as Guest Editor of 30 special issues in top-level journals. He has served as General Chair and TPC Co-Chair in several international conferences and workshops. He serves as Associate Editor in 15 international journals. He has been recipient of the best paper award at the DATE 2011 and the HiPEAC paper award 2014. He is member of the HiPEAC and IEEE Senior Member. Since 2017, he is having active research collaboration with IIT Guwahati through GIAN and SPARC projects. Maurizio Palesi-Short Bio, Maurizio Palesi- google scholar

• Workshop will be conducted in online mode through Microsoft Teams.
• Total duration of the workshop is 12 hours, spanning across four Fridays.
• Date: 18.06.2021, 25.06.2021, 02.07.2021, 09.07.2021 (All Fridays)
• There will be 2 sessions of 90 minutes duration on each day.
• Session 1: 1:00pm - 2.30pm, Session 2: 3:00pm - 4.30pm (IST)

The workshop is open to

• UG, PG, and Ph.D Students as well as Faculty from CSE/ECE/EEE/IT background.
• Technical personnel from R&D organisations/industries and technical staff working in R&D projects.

• There is NO REGISTRATION FEE. Only limited seats are there and will be filled by First Come First Serve Basis.
• Interested candidates are requested to submit the Application Registration Form on or before 13.06.2021. One person can fill the registration form only once.
• Application Registration Form
• Provisional list of shortlisted candidates will be displayed on this website on 10.06.2021 (Round-1) based on applications received till then.
• Candidates shortlisted after Round-1 have to confirm their seats before the due date as per the directions given.
• Based on availability of seats, another round of provisional candidates will be displayed on this website on 14.06.2021 (Final round).
• Candidates shortlisted after final round, have to confirm their seat before the due date as per the directions given.
• Candidates who have submitted their application are requested to check this website on 10.06.21 and 14.06.2021 for completing the confirmation process.
• Microsoft Teams link to join the workshop will be emailed to only those candidates who confirm their registration.
• E-certificates will be provided to only those participants who attend all sessions of the workshop.