Course Code: CS577
Course Name: C-Based VLSI Design: Synthesis, Optimization and Verification
Prerequisites: NIL
Syllabus: Overview:
The C-Based design has many advantages compared to traditional RTL design. First, it increases the design productivity, which allows design teams to meet the increasingly stringent time-to-market requirements. Second, the ability to create smaller designs compared to hand-coded RTL due to its ability to maximize resource sharing. Lastly the possibility of generating a set of micro-architectures with different area vs. performance trade-offs without having to modify the original behavioral description, also called Design Space Exploration (DSE) are some of them. This course focuses on all aspects of automatic hardware synthesis from C-code using high-level synthesis.

Course Syllabus:
Electronic Design Automation flow: Overview of high-level synthesis, logic synthesis and physical synthesis;
High-level Synthesis (HLS) Fundamentals: Overview HLS flow, Scheduling Techniques, Resource sharing and Binding Techniques, Data-path and Controller Generation Techniques;
Impact of C-coding style on Hardware: Data types, Synthesis of Loops, Functions, RAM, ROM, Shift register inference from arrays;
Impact of Compiler Optimization in HLS results: Impact of Compiler optimizations like copy propagation, constant propagation, common sub-expression elimination, loop transformations, code motions, etc., in HLS results;
Advanced Topics: Relative Scheduling, IO scheduling modes - cycle fixed scheduling modes, super-fixed scheduling modes, free-floating scheduling mode, Pipelining, Handshaking, System Design, High-Level Synthesis for FPGA;
RTL Optimizations Techniques: Various optimization techniques to improve latency, area and power in C-based VLSI designs;
High-level Synthesis Verification: Simulation based verification, Translation validation. Equivalence Checking between C and RTL;
Texts:
1. G. De Micheli. Synthesis and optimization of digital circuits, McGraw Hill, India Edition, 2003.
2. J. P. Elliot, Understanding Behavioural Synthesis: A Practical guide to High-level Synthesis, Springer, 2nd edition, 2000.
3. Steve Kilts, Advanced FPGA Design, Wiley, 2007.
References:
1. D. D. Gajski, N. D. Dutt, A.C.-H. Wu and S.Y.-L. Lin, High-Level Synthesis: Introduction to Chip and System Design, Springer, 1st edition, 1992.
2. Mike Fingeroff, High-Level Synthesis Blue Book, Mentor Graphics Corporation, 2010.
3. Philippe Coussy and Adam Morawiec, High-level Synthesis from Algorithm to Digital Circuit, Springer, 2008.
4. David. C. Ku and G. De Micheli, High-level Syntehsis of ASICs Under Timing and Synchronization Constraints, Kluwer Academic Publishers, 1992.
5. K. Parhi: VLSI Digital Signal Processing Systems: Design and Implementation, Jan 1999, Wiley.
6. M. Huth and M. Ryan, Logic in Computer Science: Modelling and Reasoning about Systems, 2nd Ed, Cambridge University Press, 2004.
7. T. F. Melham, Higher Order Logic and Hardware Verification, Cambridge University Press, 1993.