OpenROAD for Low-cost ASIC Design for Rapid Innovation

Outcome

The workshop on Open source EDA Design tool, OpenROAD is organized to bring together researchers, developers, and users to discuss advancement, share share knowedge and collaborate on open-source tool for chip design. After completion of this workshop, participants would be able to design digital circuits through VLSI backend flow.

Workshop Content

  • ● Introduction to VLSI Backend Flow
  • ● Stages and Sign-off Checks Overview
  • ● OpenROAD Design Flow
  • ● Detailed VLSI Backend Flow
  •                ● RTL Synthesis
  •                ● Floorplanning
  •                ● Placement
  •                ● Static Timing Analysis
  •                ● Clock Tree Synthesis
  •                ● Routing
  •                ● GUI
  •                ● OpenROAD for PPA
  • ● Hands-on
  •                ● Installation of the OpenROAD Tool.
  •                ● Input files
  •                ● RTL synthesis
  •                ● Sanity Checks
  •                ● Floorplan and Placement
  •                ● Post-placement Timing Analysis
  •                ● Clock Tree Synthesis (CTS)
  •                ● Post-CTS Timing Analysis
  •                ● Routing and DRC/LVS Check.
Workshop Schedule

    Coming soon