CS 533: ML for EDA

Instructor

• Dr. Chandan Karfa

• Dr. Sukanta Bhattacharjee

Class Timing and Venue:

• Slot G in timetable for Electives

• Wednesday: 12PM-12:55PM, Thursday: 12PM-12:55PM, Friday: 12PM-12:55PM

• Venue: 5G2, Core 5

Teaching Assistants

Syllabus

• ML for HLS: HLS steps - Scheduling, allocation, binding, RTL generation, ML for resource estimation, ML for Scheduling, ML for Design space exploration in HLS;

• ML for logic optimization: Two-level (K-map, Tabular method), Multiple level (Algebraic model), Logic representation using and inverter graph (AIG), Optimization (ABC as a case study). ML techniques (Supervised and Reinforcement) for logic optimization (ABC as a case study)

• ML for Technology mapping: ASIC and FPGA technology mapping algorithms, Technology mapping with ABC, ML techniques (supervised) for technology mapping with ABC.

• ML for Verification, Test and Security: Assertion-based verification, ML for verification, LLM-based assertion generation, LLM based test pattern generation, LLM for EDA, LLM for Security.

Text Books

• [MLEDA] Machine Learning Applications in Electronic Design Automation, Springer, 2022 (Editors: H. Ren and J. Hu)

• [Micheli] G. De Micheli. Synthesis and optimization of digital circuits, McGraw Hill, India Edition, 2003.

• [Sherwani] N. A. Sherwani, Algorithms for VLSI Physical Design Automation, Bsp Books Pvt. Ltd., 3rd edition, 2005.

• Various Research Papers.

References

• C. M. Bishop, Pattern Recognition and Machine Learning, Springer, 2006.

• R. S. Sutton and A. G. Brato, Reinforcement Learning: An Introduction, MIT Press, 2018

Grade Calculation

• Project: 30%

• Quizzes and class participation: 15%

• Mid-Sem: 25%

• End-Sem: 30%

Classes

Project Presentation Schedule

Evaluation Schedule