Shakshat Virtual Lab
INDIAN INSTITUTE OF TECHNOLOGY GUWAHATI
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CMOS Inverter
Theory
Self Evaluation
Procedure
Simulator
Assignment
Reference
Video
1.The maximum and minimum logic levels of a static CMOS inverter depends on
a) The size of the transistors
b)The Vt of the transistors
c) The load capacitance
d) None of the above
2. Which of the following statement is NOT TRUE for a CMOS inverter?
a) Highest output level will be Vdd
b) Lowest output level will be ground
c) The output impedance will be low
d)The output will be very sensitive to noise and disturbances
3. If the pMOS transistor size is increased with respect to the nMOS size, what happen to the tpLH of the inverter?
a) tpLH will increase
b)tpLH will decrease
c) tpHL will not change
d) None of the above
4. What happens to delay if you increase load capacitance?
a) no change
b) delay increases
c) delay decreases
d) None of the above
5.Which of the following is TRUE at the switching threshold of a static CMOS inverter?
a) Input voltage is equal to output voltage
b) nMOS and pMOS are in saturation mode
c) Vds=Vgs for both devices
d) All the above
