Virtual lab

4x1 Multiplexer

1.Which of the following is the correct output expression for an 4x1 MUX? [Given D0, D1, D2, D3 are the data inputs and S0, S1 are the select inputs].

a) Y = D0*D1*S0 + D2*D3*S1

b)Y = D0*S1'*S0' + D1*S1'*S0 + D2*S1*S0' + D3*S1*S0

c) Y = D0*S0' + D1*S1' + D2*S0 + D3*S1

d) Y = D0*D1*S0 + D2*D3*S1 + D0'*D1'*S0 + D2'*D3'*S1

2.Which of the following is NOT TRUE about a multiplexer?

a) For a 2^n input MUX, there are n output lines

b) MUX is a combinational circuit

c) MUX can be implemented using three-state gates

d) Apart from input and output lines, it has selection lines also

3. To implement an 8x1 MUX using 2x1 MUXs alone, we require ____ number of them.

a)4

b) 6

c)7

d) 8

4. The advantage of using transmission gate logic over pass transistor logic is

a) The number of transistors is reduced

b) The primary inputs only drive the gate terminals of the MOSFET

c) It gives a solution to the voltage-drop problem

d) They have no associated series resistances

5. In a MUX based on nMOS pass transistor logic, the maximum output voltage obtained is

a) Vdd

b) Vdd-Vtn

c) Vdd-2*Vtn

d) Vdd/2

Shakshat Virtual Lab

INDIAN INSTITUTE OF TECHNOLOGY GUWAHATI