Shakshat Virtual Lab
INDIAN INSTITUTE OF TECHNOLOGY GUWAHATI
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1.Which configuration of latches will result in a rising edge register?
a) negative latch followed by a positive latch
b) negative latch followed by a negative latch
c) positive latch followed by a positive latch
d) positive latch followed by a negative latch
2.The hold time of the register is
a) the time output must be held stable after the rising edge of the clock
b) the time output must be held stable before the rising edge of the clock
c) the time input must be held stable after the rising edge of the clock
d) the time input must be held stable before the rising edge of the clock
3.The set up time of a register is
a) the time after the rising edge of the clock that the input data must be valid
b) the time before the rising edge of the clock that the input data must be valid
c) the time after the rising edge of the clock that the output data must be valid
d) the time before the rising edge of the clock that the output data must be valid
4. For the correct operation of a shift register, which of the following conditions are important? (a) Clock period > setup time + hold time, (b) Clock to output delay > hold time.
a) (a) only
b) (b) only
c) both (a) and (b)
d) neither of them matter
5. For the proper operation of a sequential circuit, which of the following condition need to be satisfied?
a) T > clock_to_output_delay + logic_circuit_propagation_delay
b) T > clock-to-output-delay + logic-circuit-propagation_delay + set-up_time
c) T > clock-to-output-delay + logic_circuit_propagation_delay + hold_time
d) T > clock_to_output_delay + hold_time + set_up_time
