dakshgurukul@iitg.ac.in
+91-9395618834
(Time: 10:00 am to 5:30 pm, Monday to Friday)
(Time: 10:00 am to 5:30 pm, Monday to Friday)
The Executive Certification on Complete ASIC Design Flow is a specialized program designed to equip professionals with industry-relevant ASIC verification skills. The course covers digital circuits, system design, verification methodologies, and industry-standard tools to ensure a comprehensive learning experience.
✅Hands-on experience with MAGIC, SPICE, Verilog, SystemVerilog, UVM, and PERL.
✅Practical implementation of logic circuits, memory design, and finite state machines.
✅Exposure to design verification, RTL synthesis, static timing analysis, and DFT.
✅Real-world applications in Ethernet MAC core verification and AXI protocol testing.
✅Coverage of physical design, PnR flow, and tapeout processes.
VLSI professionals, graduate students, and engineers in chip design.
✅Develop proficiency in ASIC design, verification, and RTL synthesis.
✅Gain expertise in SystemVerilog, UVM, and STA methodologies.
✅Understand PnR, physical verification, and sign-off processes.
✅Industry-focused curriculum with hands-on labs and projects.
✅Certification for enhanced job prospects in semiconductor industries.
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Daksh Gurukul,1st Floor,
Technology Complex
Indian Institute of Technology Guwahati
Guwahati, Assam-781039
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