dakshgurukul@iitg.ac.in
+91-9395618834
(Time: 10:00 am to 5:30 pm, Monday to Friday)
(Time: 10:00 am to 5:30 pm, Monday to Friday)
The Executive Certification on VLSI Physical Design and Signoff is a specialized program designed for professionals and students aiming to gain expertise in the physical design and signoff process of VLSI chip development.
The course begins with RTL Synthesis, covering logic vs. physical design, synthesis steps, constraints handling, and logical equivalence checks. Static Timing Analysis (STA) follows, introducing key concepts such as setup/hold time, clock skew, jitter, propagation delay, and advanced techniques like On-Chip Variation (OCV) and signal integrity analysis.
The PnR (Place and Route) Flow module includes floorplanning, placement, clock tree synthesis, routing, and optimization techniques to ensure efficient chip design. The final module, Signoff and Tapeout, focuses on the verification process, including static timing analysis, physical verification (DRC, LVS, ERC), power analysis, and netlist hand-off between design stages.
The program offers hands-on experience with industry-standard tools, preparing participants for real-world challenges in VLSI design. By the end of the course, learners will have a deep understanding of the methodologies used in modern semiconductor design and manufacturing.
This certification is ideal for engineers, researchers, and students looking to advance their careers in VLSI Physical Design and Signoff.
VLSI Digital Integrated Circuits
VLSI Digital Integrated CircuitsVLSI DSPIntroduction to Scripting
VLSI DSPIntroduction to Scripting
Introduction to Scripting
RTL Synthesis
Static Timing Analysis
PnR flow in PD
Sign-Off and Tapeout Process
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Daksh Gurukul,1st Floor,
Technology Complex
Indian Institute of Technology Guwahati
Guwahati, Assam-781039
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