Hi, Welcome to my webpage

Our paper titled "DRackSim: Simulating CXL-enabled Large-Scale Disaggregated Memory Systems" is accepted at SIGSIM PADS'24

I am part of the Multicore Architecture Research Systems (MARS) Lab, under the supervision of       Dr. John Jose and co-supervision of Dr. T. Venkatesh . My broader area of research lies in computer architecture and operating systems.

Currently, I am working towards "Memory Disaggregation in Data Centers" as a part of my P.hD. research. Due to un-availability of hardware support and CXL interconnects, I had developed a cycle-level simulation framework DRackSim for experimentation of Scalable Disaggregated Pooled Memory Systems. Here is the link of my github Repo

Apart from this, I am exploring Chiplet-based IMC accelerators and had been working on few research problems with my lab-mate.