C6 Using Isoefficiency as a Metric to Assess Disaggregated Memory Systems for High Performance Computing
Anusha Devulapally, Mahantesh Halappanavar, Amit Puri, Vijaykrishnan Narayanan and Andres Marquez
10th International Symposium on Memory Systems [MEMSYS-2024], Washington, DC, USA, 2024.
(To Appear)
C5 DRackSim: Simulating CXL-enabled Large-Scale Disaggregated Memory Systems Amit Puri, Kartheek Bellamkonda, Kailash Narreddy, John Jose, Tamarapalli Venkatesh, Vijaykrishnan Narayanan
38th ACM SIGSIM Conference on Principles of Advanced Discrete Simulation [SIGSIM PADS-2024], Atlanta, Georgia, USA, 2024.
DOI
C4 Performance Impact of Architectural Parameters on Chiplet-Based IMC Accelerators
Abir Banerjee, Amit Puri, Kushagra Varshney, John Jose
20th India Council International Conference [INDICON-2023], Hyderabad, India, December, 2023.
DOI
C3 Understanding the Performance Impact of Queue-Based Resource Allocation in Scalable Disaggregated Memory Systems Amit Puri, Abir Banerjee, John Jose, Tamarapalli Venkatesh
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip [MCSOC-2023], Singapore, December, 2023.
DOI
C2 A Practical Approach For Workload-Aware Data Movement in Disaggregated Memory Systems Amit Puri, Kartheek Bellamkonda, Kailash Narreddy, John Jose, Venkatesh Tamarapalli
Proceedings of the 35th IEEE International Symposium on Computer Architecture and High Performance Computing [SBAC-PAD-2023], Porto Alegre, Brazil, October, 2023.
DOI
C1 Design and Evaluation of a Rack-Scale Disaggregated Memory Architecture For Data Centers Amit Puri, John Jose, Tamarapalli Venkatesh
Proceedings of 24th IEEE International Conference on High Performance Computing and Communications [HPCC-2022], Chengdu, China, December, 2022.
DOI
Communicated
Amit Puri, John Jose, Tamarapalli Venkatesh, Vijaykrishnan Narayanan CosMoS: Architectural Support for Cost-Effective Data Movement in a Scalable Disaggregated Memory Systems
