Hi, Welcome to my webpage

"Our Paper Titled "CosMoS: Architectural Support for Cost-Effective Data Movement in a Scalable Disaggregated Memory Systems" has been accepted at ACM Journal on Emerging Technologies in Computing Systems (ACM JETC), March 2025

I am working at AMD (Advanced Micro Devices) as a senior design engineer from May 2024 onwards. Prior to this, I was part of the Multicore Architecture Research Systems (MARS) Lab, under the supervision of Dr. John Jose and Dr. T. Venkatesh . My broader area of research lies in Computer Systems Architecture and Design.

During my Ph.D, I worked on "Design, Analysis and Optimization of Large-Scale Disaggregated Memory Systems for Data Centers". Due to un-availability of CXL interconnect and hardware support, I developed an open-source Cycle-Level Architectural Simulator framework DRackSim for experimentation of large scale CXL-based Pooled Memory Systems. Here is the link of my github Repo.

Apart from this, I am also exploring Chiplet-based IMC accelerators and had been working on few research problems with my lab-mate.