Virtual lab

Logic Gates

1.Which of the following gate will result in larger pMOS transistor size?

a) NAND

b) NOR

c) Both NAND and NOR

d) None of the above

2.Which of the following is preferred for realizing pull down network (PDN)?

a) nMOS

b) pMOS

c) Both nMOS and pMOS

d) None of the above

3. Assuming an electron-hole mobility ratio 2, determine the size of the pMOS and nMOS transistors in 180nm technology for a static NOR gate with equal tpLH and tpHL values.

a) (W/L)n=(W/L)p=360/180

b) (W/L)n=360/180, (W/L)p=720/180

c) (W/L)n=1440/180, (W/L)p=360/180

d) (W/L)n=360/180, (W/L)p=1440/180

4. Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the output?

a) Input A should go to the nMOS transistor closer to output

b) Input B should go to the nMOS transistor closer to output

c) Doesn't make any difference

d) None of the above

5. Which of the following statement is NOT TRUE about the CMOS dynamic logic circuit design?

a) A clock signal is used to evaluate combinational logic

b) Dynamic logic is faster than static logic

c) Dynamic logic has low switching probability compared to static logic

d) Dynamic logic is not suitable for low frequency application

Shakshat Virtual Lab

INDIAN INSTITUTE OF TECHNOLOGY GUWAHATI