Syllabus (Core): M.Tech

Signal Processing Algorithms and Architectures

Code: EE 520 | L-T-P-C : 3-0-0

Orthogonal transforms: DFT, DCT and Haar; Properties of DFT; Computation of DFT: FFT and structures, Decimation in time, Decimation in frequency; Linear convolution using DFT; Digital filter structures: Basic FIR/IIR filter structures, FIR/IIR Cascaded lattice structures, Parallel allpass realization of IIR transfer functions, Sine- cosine generator; Computational complexity of filter structures; Multirate signal processing: Basic structures for sampling rate conversion, Decimators and Interpolators; Multistage design of interpolators and decimators; Polyphase decomposition and FIR structures; Computationally efficient sampling rate converters; Arbitrary sampling rate converters based on interpolation algorithms: Lagrange interpolation, Spline interpolation; Quadrature mirror filter banks; Conditions for perfect reconstruction; Applications in subband coding; Digital Signal Processors introduction: Computational characteristics of DSP algorithms and applications; Techniques for enhancing computational throughput: Harvard architecture, parallelism, pipelining, dedicated multiplier, split ALU and barrel shifter; TMS320C64xx architecture: CPU data paths and control, general purpose register files, register file cross paths, memory load and store paths, data address paths, parallel operations, resource constraints.

Texts / References:

1. R. Chassaing and D. Reay, Digital signal processing and applications with TMS320C6713 and TMS320C6416, Wiley, 2008.
2. S. K. Mitra, Digital Signal Processing: A Computer Based Approach, 3rd Edn., TMH, 2008.
3. J. G. Proakis and D. G. Manolakis, Digital Signal Processing:
4. Principles, Algorithms and Applications, Pearson Prentice Hall, 2007