Key Research Areas : VLSI Architectures for Signal Processing, Machine Learning and Communication Algorithms, Digital IC Design, Adaptive Signal Processing and Biomedical Signal Processing.
Phone No: +91-361-2582520 (O) | Email: rafiahamed@iitg.ac.in| Room No: 0304
Research/Project title: VLSI Algorithms and Architectures for Semantic Segmentation
Co-Supervisor: NA
Status: Current
Research/Project title: Design and Analysis of Countermeasures Against Power Analysis Attacks
towards IoT Applications
Co-Supervisor: NA
Status: Current
Research/Project title: Development of Real-time Semantic Image Segmentation Algorithm for Edge Devices
Year of Joining: 2018
Co-Supervisor: mkb@iitg.ac.in
Status: Current
Research/Project title: Development of Efficient Algorithms and VLSI Architectures for Brain Disorders
Year of Joining: 2019
Co-Supervisor: mkb@iitg.ac.in
Status: Current
Research/Project title: EEG Based Emotion Recognition
Year of Joining: 2019
Co-Supervisor: NA
Status: Current
Research/Project title: Development of Efficient Algorithms and VLSI Architectures for
Sleep Stage Classification
Year of Joining: 2020
Co-Supervisor: NA
Status: Current
Research/Project title: Hardware Design and Implementation of Massive MIMO Baseband Processing for 5G and
Beyond
Year of Joining: 2021
Co-Supervisor: roypaily@iitg.ac.in
Status: Current
Research/Project title: EEG Signal Processing
Year of Joining: 2022
Co-Supervisor: NA
Status: Current
Research/Project title: VLSI
Year of Joining: 2023
Co-Supervisor: NA
Status: Current
Research/Project title: VLSI
Year of Joining: 2023
Co-Supervisor: NA
Status: Current
Research/Project title: High Performance Architectures for Adaptive Equalizers using Distributed Arithmetic
Year of Complete: 2015
Co-Supervisor: NA
Current Placement: NIT Calicut
Current Address: Assistant Professor, Dept. of ECE, NIT Calicut
Status: Completed
Research/Project title: Efficient Subspace based Techniques for Processing Single Channel Electroencephalogram Signals
Year of Complete: 2017
Co-Supervisor: NA
Current Placement: Post Doctoral Associate
Current Address: Broad Institute of MIT and Harvard, Boston, USA
Status: Completed
Research/Project title: Low Power VLSI Architectures for WBAN Cryptographic Algorithms
Year of Complete: 2018
Co-Supervisor: NA
Status: Completed
Research/Project title: High Performance Techniques for Low-Voltage Bulk-Driven Circuits in 65nm CMOS Process
Year of Complete: 2018
Co-Supervisor: NA
Status: Completed
Research/Project title: Power Efficient Motion Estimation Algorithms and Architectures for HEVC/H.265
Year of Complete: 2019
Co-Supervisor: NA
Status: Completed
Research/Project title: Low-Complexity Distributed Arithmetic based Pipelined VLSI Architectures for LMS Adaptive Filters
Year of Complete: 2019
Co-Supervisor: NA
Status: Completed
Research/Project title: Design of IR-UWB Transmitter and Receiver for IEEE 802.15.6 Wireless Body Area Network System
Year of Complete: 2019
Co-Supervisor: anilm@iitg.ac.in
Status: Completed
Research/Project title: Design and Implementation of Continuous Flow FFT Processors for OFDM in Wireless GigaHertz Standards
Year of Complete: 2023
Co-Supervisor: NA
Status: Completed
Research/Project title: Design and Implementation of Hardware-Efficient VLSI Architectures for FFT Algorithms
Co-Supervisor: NA
Status: Completed
Research/Project title: VLSI Implementation of Training Accelerators for Decision Tree Algorithm
Year of Complete: 2023
Co-Supervisor: pguha@iitg.ac.in
Status: Completed
Research/Project title: Medical Image Processing
Year of Joining: 2020
Year of Complete: 2022
Co-Supervisor: NA
Status: Completed
Department of Electronics and Electrical Engineering Indian Institute of Technology Guwahati Guwahati, Assam, India.PIN-781 039. Email: eeeoff@iitg.ac.in Telehone: +91-361-2582550 Fax: +91-361-2582542 +91-361-2690762
+91-361-2582550
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